The search functionality is under construction.

Keyword Search Result

[Keyword] reliability(282hit)

81-100hit(282hit)

  • Re-Scheduling of Unit Commitment Based on Customers' Fuzzy Requirements for Power Reliability

    Bo WANG  You LI  Junzo WATADA  

     
    PAPER-Fundamentals of Information Systems

      Vol:
    E94-D No:7
      Page(s):
    1378-1385

    The development of the electricity market enables us to provide electricity of varied quality and price in order to fulfill power consumers' needs. Such customers choices should influence the process of adjusting power generation and spinning reserve, and, as a result, change the structure of a unit commitment optimization problem (UCP). To build a unit commitment model that considers customer choices, we employ fuzzy variables in this study to better characterize customer requirements and forecasted future power loads. To measure system reliability and determine the schedule of real power generation and spinning reserve, fuzzy Value-at-Risk (VaR) is utilized in building the model, which evaluates the peak values of power demands under given confidence levels. Based on the information obtained using fuzzy VaR, we proposed a heuristic algorithm called local convergence-averse binary particle swarm optimization (LCA-PSO) to solve the UCP. The proposed model and algorithm are used to analyze several test systems. Comparisons between the proposed algorithm and the conventional approaches show that the LCA-PSO performs better in finding the optimal solutions.

  • Shaka: User Movement Estimation Considering Reliability, Power Saving, and Latency Using Mobile Phone

    Arei KOBAYASHI  Shigeki MURAMATSU  Daisuke KAMISAKA  Takafumi WATANABE  Atsunori MINAMIKAWA  Takeshi IWAMOTO  Hiroyuki YOKOYAMA  

     
    PAPER

      Vol:
    E94-D No:6
      Page(s):
    1153-1163

    This paper proposes a method for using an accelerometer, microphone, and GPS in a mobile phone to recognize the movement of the user. Past attempts at identifying the movement associated with riding on a bicycle, train, bus or car and common human movements like standing still, walking or running have had problems with poor accuracy due to factors such as sudden changes in vibration or times when the vibrations resembled those for other types of movement. Moreover, previous methods have had problems with has the problem of high power consumption because of the sensor processing load. The proposed method aims to avoid these problems by estimating the reliability of the inference result, and by combining two inference modes to decrease the power consumption. Field trials demonstrate that our method achieves 90% or better average accuracy for the seven types of movement listed above. Shaka's power saving functionality enables us to extend the battery life of a mobile phone to over 100 hours while our estimation algorithm is running in the background. Furthermore, this paper uses experimental results to show the trade-off between accuracy and latency when estimating user activity.

  • A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors

    Makoto SUGIHARA  

     
    PAPER

      Vol:
    E94-C No:4
      Page(s):
    477-486

    Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become a matter of concern as integrated circuits continue to shrink. It is getting more and more important to take reliability requirements into account even for consumer products. This paper presents a dynamic continuous signature monitoring (DCSM) technique for high reliable computer systems. The DCSM technique dynamically generates reference signatures as well as runtime ones during executing a program. The DCSM technique stores the generated signatures in a signature table, which is a small storage circuit in a microprocessor, unlike the conventional static continuous signature monitoring techniques and contributes to saving program or data memory space that stores the signatures. Our experiments showed that our DCSM technique protected 1.4-100.0% of executed instructions depending on the size of signature tables.

  • Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design

    Norio SADACHIKA  Shu MIMURA  Akihiro YUMISAKI  Kou JOHGUCHI  Akihiro KAYA  Mitiko MIURA-MATTAUSCH  Hans Jurgen MATTAUSCH  

     
    PAPER-Semiconductor Materials and Devices

      Vol:
    E94-C No:3
      Page(s):
    361-367

    The long-standing problem of predicting circuit performance variations without a huge number of statistical investigations is demonstrated to be solvable by a surface-potential-based MOSFET model. Direct connection of model parameters to physical device parameters reflecting process variations and the reduced number of model parameters are the enabling key model properties. It has been proven that the surface-potential-based model HiSIM2 is capable of reproducing measured I-V and its derivatives' variations with those of device/process related model parameters. When used to predict 51-stage ring oscillator frequency variation including both inter- and intra-chip variation, it reproduces measurements with shortened simulation time.

  • Quality-Based Event Reliability Protocol in Wireless Sensor Networks

    Euisin LEE  Soochang PARK  Hosung PARK  Sang-Ha KIM  

     
    LETTER-Network

      Vol:
    E94-B No:1
      Page(s):
    293-296

    Quantity-based event reliability protocols have been proposed for reliable event detection in wireless sensor networks. They support the event reliability by achieving the desired number of data packets successfully transmitted from sensor nodes sensing an event to a sink by controlling the transport process. However, since many data collisions and buffer overflows frequently happen due to data congestions on limited data delivery paths from an event to a sink, the quantity-based event reliability protocols are hard to achieve the desired number due to lost data packets. Thus, this letter proposes a Quality-based Event Reliability Protocol (QERP) utilizing a property that the data packets from sensor nodes have different Contribution Degree (CD) values for event detection according to their environmental conditions. QERP selects sensor nodes to forward their data packets according to CD, and differentially transports the data packets by CD-based buffer management and load balancing.

  • Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures

    Takashi IMAGAWA  Masayuki HIROMOTO  Hiroyuki OCHI  Takashi SATO  

     
    PAPER-High-Level Synthesis and System-Level Design

      Vol:
    E93-A No:12
      Page(s):
    2524-2532

    This paper proposes a reliability evaluation environment for coarse-grained reconfigurable architectures. This environment is designed so that it can be easily extended to different target architectures and applications by automating the generation of the simulation inputs such as HDL codes for fault injection and configuration information. This automation enables us to explore a huge design space in order to efficiently analyze area/reliability trade-offs and find the best solution. This paper also shows demonstrative examples of the design space exploration of coarse-grained reconfigurable architectures using the proposed environment. Through the demonstrations, we discuss relationship between coarse-grained architectures and reliability, which has not yet been addressed in existing literatures and show the feasibility of the proposed environment.

  • On Synthesizing a Reliable Multiprocessor for Embedded Systems

    Makoto SUGIHARA  

     
    PAPER-High-Level Synthesis and System-Level Design

      Vol:
    E93-A No:12
      Page(s):
    2560-2569

    Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to soft errors, has not been taken into account in the conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor as a vulnerability measure for computer systems so that we evaluate task-wise reliability over various processor structures. Next we build a mixed integer linear programming (MILP) model for minimizing the chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

  • Dual Evanescently Coupled Waveguide Photodiodes with High Reliability for over 40-Gbps Optical Communication Systems Open Access

    Kazuhiro SHIBA  Yasuyuki SUZUKI  Sawaki WATANABE  Tadayuki CHIKUMA  Takeshi TAKEUCHI  Kikuo MAKITA  

     
    PAPER-Lasers, Quantum Electronics

      Vol:
    E93-C No:12
      Page(s):
    1655-1661

    For over 40-Gbps optical communication systems, phase coded modulation formats, like differential phase shift keying (DPSK) and quadrature phase shift keying (QPSK), are very important for signal frequency efficiency and long-reach transmission. In such systems, differential receivers which regenerate phase signals are key components. Dual Photo Diodes (dual PDs) are key semiconductor devices which determine the receiver performance. Each PD of the dual PDs should realize high speed performance, high responsibility and high input power operation capability. Highly symmetrical characteristics between the two PDs should be also realized, thus the dual PDs are desired to be monolithically integrated to one chip. In this paper, we describe the design, fabrication, characteristics and reliability of monolithically integrated dual evanescently coupled waveguide photodiodes (EC-WG-PDs) for the purpose described above. The structure of the EC-WG-PDs offers the attractive advantages of high speed performance, high responsivity and high input power operation. Furthermore, their fabrication process is suitable for the integration of two PDs on one ship. First, the optimization was done for high products of 3-dB bandwidth and responsivity for 43-Gbps DPSK receivers. Excellent characteristics (50 GHz bandwidth with a responsivity of 0.95 A/W), and high reliability were demonstrated. The other type of optimization was done for ultra high speed operation up to 100-Gbps. The fabricated PDs exhibited the 3 dB-bandwidth of 80 GHz with a responsivity of 0.25 A/W. Furthermore, 43-Gbps RZ-DPSK receivers including the dual EC-WG-PDs based on the former optimization and differential transimpedance amplifiers (TIAs) newly developed for the purpose were also presented. Clear and symmetrical eye openings were observed for both ports. The OSNR characteristics exhibited 14.3 dB at a bit error rate of 10-3 that is able to be recovery with FEC. These performances are enough for practical use in 43-Gbps RZ-DPSK systems.

  • The Software Reliability Model Using Hybrid Model of Fractals and ARIMA

    Yong CAO  Qingxin ZHU  

     
    LETTER-Software Engineering

      Vol:
    E93-D No:11
      Page(s):
    3116-3119

    The software reliability is the ability of the software to perform its required function under stated conditions for a stated period of time. In this paper, a hybrid methodology that combines both ARIMA and fractal models is proposed to take advantage of unique strength of ARIMA and fractal in linear and nonlinear modeling. Based on the experiments performed on the software reliability data obtained from literatures, it is observed that our method is effective through comparison with other methods and a new idea for the research of the software failure mechanism is presented.

  • Highly Reliable and Drivability-Enhanced MOS Transistors with Rounded Nanograting Channels

    Takashi ITO  Xiaoli ZHU  Shin-Ichiro KUROKI  Koji KOTANI  

     
    PAPER-Semiconductor Materials and Devices

      Vol:
    E93-C No:11
      Page(s):
    1638-1644

    The structure of the nanograting channel MOSFET was optimized by simply rounding the corners of the nanogratings. The current drivabilities of the optimized nanograting channel MOSFETs were enhanced by about 20% and 50% for both n-channel and p-channel MOSFETs, respectively. The mobility changes were analyzed on the basis of channel stress as well as theoretical change of mobilities by various surface orientations. The internal compressive stress of 0.23% was measured in the channel. By suppressing the electric field increase at the corner edge of the nanograting channel to less than 10%, the fabricated rounded nanograting MOSFETs achieved lifetimes of NBTI and TDDB as long as those of conventional planar devices.

  • Performance of MPEG-4 Transmission over SCTP Multi-Streaming in Wireless Networks

    Li WANG  Ken'ichi KAWANISHI  

     
    PAPER-Internet

      Vol:
    E93-B No:9
      Page(s):
    2336-2347

    Stream Control Transmission Protocol (SCTP) is a new transport layer protocol for the next generation Internet. SCTP is a connection-oriented protocol that carries over TCP's features but also supports UDP-like message-oriented data transmission. In this paper, we make use of SCTP's multi-streaming feature to transmit MPEG-4 video efficiently, and evaluate its transmission performance under the policy with/without differentiated retransmission. Moreover, to enhance the communication quality, we extend SCTP multi-streaming to realize selective retransmission policy. Our extension utilizes packet-by-packet timestamps to control retransmission of lost packets. By computer simulation, we show that SCTP can (1) improve the video quality by exploiting the multi-streaming and partial reliability features, (2) enhance the video transmission quality by adjusting SCTP fast retransmit threshold, and (3) SCTP with our selective retransmission extension can further improve the whole performance.

  • A Robust Closed-Loop Transmit-Diversity Scheme with Unknown CSI Reliability

    Eunchul YOON  Joon-Tae KIM  Taewon HWANG  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E93-B No:9
      Page(s):
    2400-2406

    In a closed-loop scenario, the performance of transmit-diversity schemes for a multiple antenna system depends on the reliability of the channel state information (CSI). However, estimating the reliability of the instantaneous CSI at the transmitter is a challenging task. In this paper, we propose a robust transmit-diversity scheme for the case when the instantaneous CSI available at the transmitter is imperfect and its reliability is unknown to the transmitter. We show by simulation that our proposed scheme is efficient when the CSI reliability varies arbitrarily in every channel realization.

  • Highly Reliable PON Optical Splitters for Optical Access Networks in Outside Environments

    Hiroshi WATANABE  Noriyuki ARAKI  Hisashi FUJIMOTO  

     
    PAPER

      Vol:
    E93-C No:7
      Page(s):
    1180-1190

    Broadband optical access services are spreading throughout the world, and the number of fiber to the home (FTTH) subscribers is increasing rapidly. Telecom operators are constructing passive optical networks (PONs) to provide optical access services. Externally installed optical splitters for PONs are very important passive devices in optical access networks, and they must provide satisfactory performance as outdoor plant over long periods. Therefore, we calculate the failure rate of optical access networks and assign a failure rate to the optical splitters in optical access networks. The maximum cumulative failure rate of 18 optical splitters was calculated as 0.025 for an optical access fiber length of 2.1 km and a 20-year operating lifetime. We examined planar lightwave circuit (PLC) type optical splitters for use as outside plant in terms of their optical characteristics and environmental reliability. We confirmed that PLC type optical splitters have sufficient optical performance for a PON splitter and sufficient reliability as outside plant in accordance with ITU-T standard values. We estimated the lifetimes of three kinds of PLC type optical splitters by using accelerated aging tests. The estimated failure rate of these splitters installed in optical access networks was below the target value for the cumulative failure rate, and we confirmed that they have sufficient reliability to maintain the quality of the network service. We developed 18 optical splitter modules with plug and socket type optical connectors and optical fiber cords for optical aerial closures designed for use as outside plant. These technologies make it easy to install optical splitters in an aerial optical closure. The optical splitter modules have sufficient optical performance levels for PONs because the insertion loss at the commercially used wavelengths of 1.31 and 1.55 µm is less than the criterion established by ITU-T Recommendation G.671 for optical splitters. We performed a temperature cycling test, and a low temperature storage and damp heat test to confirm the long-term reliability of these modules. They exhibited sufficient reliability as regards heat and moisture because the maximum loss change was less than 0.3 dB.

  • New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer

    Joung-Yeal KIM  Su-Jin PARK  Yong-Ki KIM  Sang-Keun HAN  Young-Hyun JUN  Chilgee LEE  Tae Hee HAN  Bai-Sun KONG  

     
    LETTER-Integrated Electronics

      Vol:
    E93-C No:5
      Page(s):
    709-711

    A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.

  • Design and Implementation of Hybrid MAC-Based Robust Architecture for Wireless Sensor Network

    Taeshik SHON  Eui-jik KIM  Jeongsik IN  Yongsuk PARK  

     
    LETTER-Network

      Vol:
    E93-B No:4
      Page(s):
    1016-1019

    In this letter, we propose an energy efficient hybrid architecture, the Hybrid MAC-based Robust Architecture (HMR), for wireless sensor networks focusing on MAC layer's scheduling and adaptive security suite as a security sub layer. A hybrid MAC layer with TDMA and CSMA scheduling is designed to prolong network life time, and the multi-channel TDMA based active/sleep scheduling is presented. We also present the security related functionalities needed to employ a flexible security suite to packets dynamically. Implementation and testbed of the proposed framework based on IEEE 802.15.4 are shown as well.

  • The Software Reliability Model Based on Fractals

    Yong CAO  Qingxin ZHU  

     
    LETTER-Software Engineering

      Vol:
    E93-D No:2
      Page(s):
    376-379

    Fractals are mathematical or natural objects that are made of parts similar to the whole in certain ways. In this paper a software reliability forecasting method of software failure is proposed based on predictability of fractal time series. The empirical failure data (three data sets of Musa's) are used to demonstrate the performance of the reliability prediction. Compared with other methods, our method is effective.

  • Software Reliability Modeling Considering Fault Correction Process

    Lixin JIA  Bo YANG  Suchang GUO  Dong Ho PARK  

     
    LETTER-Software Engineering

      Vol:
    E93-D No:1
      Page(s):
    185-188

    Many existing software reliability models (SRMs) are based on the assumption that fault correction activities take a negligible amount of time and resources, which is often invalid in real-life situations. Consequently, the estimated and predicted software reliability tends to be over-optimistic, which could in turn mislead management in related decision-makings. In this paper, we first make an in-depth analysis of real-life software testing process; then a Markovian SRM considering fault correction process is proposed. Parameter estimation method and software reliability prediction method are established. A numerical example is given which shows that by using the proposed model and methods, the results obtained tend to be more appropriate and realistic.

  • Reliability Analysis and Modeling of ZigBee Networks

    Cheng-Min LIN  

     
    PAPER-Dependable Computing

      Vol:
    E93-D No:1
      Page(s):
    68-78

    The architecture of ZigBee networks focuses on developing low-cost, low-speed ubiquitous communication between devices. The ZigBee technique is based on IEEE 802.15.4, which specifies the physical layer and medium access control (MAC) for a low rate wireless personal area network (LR-WPAN). Currently, numerous wireless sensor networks have adapted the ZigBee open standard to develop various services to promote improved communication quality in our daily lives. The problem of system and network reliability in providing stable services has become more important because these services will be stopped if the system and network reliability is unstable. The ZigBee standard has three kinds of networks; star, tree and mesh. The paper models the ZigBee protocol stack from the physical layer to the application layer and analyzes these layer reliability and mean time to failure (MTTF). Channel resource usage, device role, network topology and application objects are used to evaluate reliability in the physical, medium access control, network, and application layers, respectively. In the star or tree networks, a series system and the reliability block diagram (RBD) technique can be used to solve their reliability problem. However, a division technology is applied here to overcome the problem because the network complexity is higher than that of the others. A mesh network using division technology is classified into several non-reducible series systems and edge parallel systems. Hence, the reliability of mesh networks is easily solved using series-parallel systems through our proposed scheme. The numerical results demonstrate that the reliability will increase for mesh networks when the number of edges in parallel systems increases while the reliability quickly drops when the number of edges and the number of nodes increase for all three networks. More use of resources is another factor impact on reliability decreasing. However, lower network reliability will occur due to network complexity, more resource usage and complex object relationship.

  • Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability

    Yuji TAKASHIMA  Kazuyuki OOYA  Atsushi KUROKAWA  

     
    PAPER-Physical Level Desing

      Vol:
    E92-A No:12
      Page(s):
    2962-2970

    As the integrated circuit technology has undergone continuous downscaling to improve the LSI performance and reduce chip size, design for manufacturability (DFM) and design for yield (DFY) have become very important. As one of the DFM/DFY methods, a redundant via insertion technique uses as many vias as possible to connect the metal wires between different layers. In this paper, we focus on redundant vias and propose an effective redundant via insertion method for practical use to address the manufacturing variability and reliability concerns. First, the results of statistical analysis for via resistance and via capacitance in some real physical layouts are shown, and the impact on circuit delay of the resistance variation of vias caused by manufacturing variability is clarified. Then, the valuation functions of delay variation, electro-migration (EM), and stress-migration (SM) are defined and a practical method concerning redundant via insertion is proposed. Experimental results show that LSI with redundant vias inserted by our method robust against manufacturing variability and reliability problems.

  • Fiber Access Networks: Reliability Analysis and Swedish Broadband Market Open Access

    Lena WOSINSKA  Jiajia CHEN  Claus Popp LARSEN  

     
    INVITED PAPER

      Vol:
    E92-B No:10
      Page(s):
    3006-3014

    Fiber access network architectures such as active optical networks (AONs) and passive optical networks (PONs) have been developed to support the growing bandwidth demand. Whereas particularly Swedish operators prefer AON, this may not be the case for operators in other countries. The choice depends on a combination of technical requirements, practical constraints, business models, and cost. Due to the increasing importance of reliable access to the network services, connection availability is becoming one of the most crucial issues for access networks, which should be reflected in the network owner's architecture decision. In many cases protection against failures is realized by adding backup resources. However, there is a trade off between the cost of protection and the level of service reliability since improving reliability performance by duplication of network resources (and capital expenditures CAPEX) may be too expensive. In this paper we present the evolution of fiber access networks and compare reliability performance in relation to investment and management cost for some representative cases. We consider both standard and novel architectures for deployment in both sparsely and densely populated areas. While some recent works focused on PON protection schemes with reduced CAPEX the current and future effort should be put on minimizing the operational expenditures (OPEX) during the access network lifetime.

81-100hit(282hit)