We are given a set S of n points in the Euclidean plane. We assume that S is in general position. A simple polygon P is an empty polygon of S if each vertex of P is a point in S and every point in S is either outside P or a vertex of P. In this paper, we consider the problem of enumerating all the empty polygons of a given point set. To design an efficient enumeration algorithm, we use a reverse search by Avis and Fukuda with child lists. We propose an algorithm that enumerates all the empty polygons of S in O(n2|ε(S)|)-time, where ε(S) is the set of empty polygons of S. Moreover, by applying the same idea to the problem of enumerating surrounding polygons of a given point set S, we propose an enumeration algorithm that enumerates them in O(n2)-delay, while the known algorithm enumerates in O(n2 log n)-delay, where a surroundingpolygon of S is a polygon such that each vertex of the polygon is a point in S and every point in S is either inside the polygon or a vertex of the polygon.

We propose a new lattice-based digital signature scheme MLWRSign by modifying Dilithium, which is one of the second-round candidates of NIST's call for post-quantum cryptographic standards. To the best of our knowledge, our scheme MLWRSign is the first signature scheme whose security is based on the (module) learning with rounding (LWR) problem. Due to the simplicity of the LWR, the secret key size is reduced by approximately 30% in our scheme compared to Dilithium, while achieving the same level of security. Moreover, we implemented MLWRSign and observed that the running time of our scheme is comparable to that of Dilithium.

In order to realize better understanding of influential order sequences of surrounding atmospheres on break arc durations of electrical contacts in DC load conditions, a quantitative mathematical model, which aims to indicate dependences of break arc durations on several gas parameters such as molecular mass, viscosity, specific heat capacity, thermal conductivity, electro-negativity, and ionization potential, was analyzed. Break arc durations of AgCdO contact pairs were measured in several kinds of surrounding atmospheres (N2, Ar, He, air, O2 and CO2) under different DC voltage and current conditions, and data fitting processes were conducted. As a result, a candidate mathematical model was established, which could indicate possible influential order sequences of surrounding atmospheres on break arc durations in the range of the tested conditions.

The Blum-Kalai-Wasserman algorithm (BKW) is an algorithm for solving the learning parity with noise problem, which was then adapted for solving the learning with errors problem (LWE) by Albrecht et al. Duc et al. applied BKW also to the learning with rounding problem (LWR). The number of blocks is a parameter of BKW. By optimizing the number of blocks, we can minimize the time complexity of BKW. However, Duc et al. did not derive the optimal number of blocks theoretically, but they searched for it numerically. Duc et al. also showed that the required number of samples for BKW for solving LWE can be dramatically decreased using Lyubashevsky's idea. However, it is not shown that his idea is also applicable to LWR. In this paper, we theoretically derive the asymptotically optimal number of blocks, and then analyze the minimum asymptotic time complexity of the algorithm. We also show that Lyubashevsky's idea can be applied to LWR-solving BKW, under a heuristic assumption that is regularly used in the analysis of LPN-solving BKW. Furthermore, we derive an equation that relates the Gaussian parameter σ of LWE and the modulus p of LWR. When σ and p satisfy the equation, the asymptotic time complexity of BKW to solve LWE and LWR are the same.

Recently, the 3-D vertical Floating Gate (FG) type NAND cell arrays with the Sidewall Control Gate (SCG), such as ESCG, DC-SF and S-SCG, are receiving attention to overcome the reliability issues of Charge Trap (CT) type device. Using this novel cell structure, highly reliable flash cell operations were successfully implemented without interference effect on the FG type cell. However, the 3-D vertical FG type cell has large cell size by about 60% for the cylindrical FG structure. In this point of view, we intensively investigate the scalability of the FG width of the 3-D vertical FG NAND cells. In case of the planar FG type NAND cell, the FG height cannot be scaled down due to the necessity of obtaining sufficient coupling ratio and high program speed. In contrast, for the 3-D vertical FG NAND with SCG, the FG is formed cylindrically, which is fully covered with surrounded CG, and very high CG coupling ratio can be achieved. As results, the scaling of FG width of the 3-D vertical FG NAND cell with S-SCG can be successfully demonstrated at 10 nm regime, which is almost the same as the CT layer of recent BE-SONOS NAND.

Because of its simple structure, many reports on the logistic map have been presented. To implement this map on computers, finite precision is usually used, and therefore rounding is required. There are five major methods to implement rounding, but, to date, no study of rounding applied to the logistic map has been reported. In the present paper, we present experimental results showing that the properties of sequences generated by the logistic map are heavily dependent on the rounding method used and give a theoretical analysis of each method. Then, we describe why using the map with a floor function for rounding generates long aperiodic subsequences.

The asymmetrical halo and dual-material gate structure is used in the surrounding-gate metal-oxide-semiconductor field effect transistor (MOSFET) to improve the performance. By treating the device as three surrounding-gate MOSFETs connected in series and maintaining current continuity, a comprehensive drain current model is developed for it. The model incorporates not only channel length modulation and impact ionization effects, but also the influence of doping concentration and vertical electric field distributions. It is concluded that the device exhibits increased current drivability and improved hot carrier reliability. The derived analytical model is verified with numerical simulation.

Recently, the 3-dimensional (3-D) vertical Floating Gate (FG) type NAND flash memory cell arrays with the Extended Sidewall Control Gate (ESCG) was proposed [7]. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high Control Gate (CG) coupling ratio with less interference capacitance and highly electrical inverted S/D technique. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions. In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG and the thickness of barrier oxide. Using the 2-dimentional (2-D) TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array.

We have studied transmission property of electron in vertical MOSFET (V-MOSFET) from the viewpoint of quantum electro-dynamics. To obtain the intuitive picture of electron transmission property through channel of the V-MOSFET, we solve the time-dependent Schrodinger equation in real space by employing the split operator method. We injected an electron wave packet into the body of the V-MOSFET from the source, and traced the time-development of electron-wave function in the body and drain region. We successfully showed that the electron wave function propagates through the resonant states of the body potential. Our suggested approaches open the quantative and intuitive discussion for the carrier dynamics in the V-MOSFET on quantum limit.

We propose a 2D display and camera arrangement for video communication systems that supports both spatial information between distant sites and user mobility. The implementation of this arrangement is called the "surrounding back screen method." The method enables users to freely come from and go into other users' spaces and provides every user with the direct pointing capability, since there is no apparent spatial barrier separating users, unlike the case of conventional video communication systems. In this paper, we introduce two properties ("sharedness" and "exclusiveness") and three parameters (a distance and two angles) to represent the geometrical relationship between two users. These properties and parameters are used to classify the shared spaces created by a video communication system and to investigate the surrounding back screen method. Furthermore, to demonstrate and explore our surrounding back screen method, we have developed a prototype system, called t-Room. Taking into account practical situations, we studied a practical case where two t-Rooms with different layouts are connected.

Halo doping profile is used in nanoscale surrounding-gate MOSFETs to suppress short channel effect and improve current driving capability. Analytical surface potential and threshold voltage models are derived based on the analytical solution of Poisson's equation for the fully depleted symmetric and asymmetric halo-doped MOSFETs. The validity of the analytical models is verified using 3D numerical simulation. The performance of the halo-doped MOSFETs are studied and compared with the uniformly doped surrounding-gate MOSFETs. It is shown that the halo-doped channel can suppress threshold voltage roll-off and drain-induced barrier lowering, and improve carrier transport efficiency. The asymmetric halo structure is better in suppressing hot carrier effect than the symmetric halo structure.

Suppose that we have a timetable of a round-robin tournament with a number of teams, and distances among their homes. The home-away assignment problem is to find a home-away assignment that minimizes the total traveling distance of the teams. We propose a formulation of the home-away assignment problem as an integer program, and a rounding algorithm based on Bertsimas, Teo and Vohra's dependent randomized rounding method [2]. Computational experiments show that our method quickly generates feasible solutions close to optimal.

This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10 nm, the gate length is 20 nm, and the oxide thickness is 1 nm, the SGT shows a subthreshold swing of 63 mV/dec and a DIBL of -17 mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71 mV/dec and 77 mV/dec, respectively, and a DIBL of -47 mV and -75 mV, respectively. By adjusting the value of the gate work function, we define the off current at VG = 0 V and VD = 1 V. When the off current is set at 1 pA/µm, the SGT can realize a high on current of 1020 µA/µm at VG = 1 V and VD = 1 V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.

In this paper, we propose a new one-dimensional (1D) integer discrete cosine transform (Int-DCT) for unified lossless/lossy image compression. The proposed 1D Int-DCT is newly designed to reduce rounding effects by minimizing number of rounding operations. The proposed Int-DCT can be operated not only lossless coding for a high quality decoded image but also lossy coding for a compatibility with the conventional DCT-based coding system. Both theoretical analysis and simulation results confirm an effectiveness of the proposed Int-DCT.

This paper analyzes program and erase mechanisms for Floating Channel type Surrounding Gate Transistor (FC-SGT) Flash memory cells for the first time. In FC-SGT Flash memory cell, control gate, floating gate, drain and source is arranged vertically on the substrate. The body region is isolated from the substrate by the bottom source region. The cell is programmed by applying a high positive voltage to the control gate electrode with drain and source electrodes grounded. Erasing is performed by applying a high positive voltage to the drain and source electrodes with the control gate electrode grounded. The physical models for program and erase operations in FC-SGT Flash memory cell are developed. Program and erase operations based on the developed physical models are simulated by utilizing a device simulator. Program and erase characteristics obtained from the device simulation agree well with the results of analytical models. The FC-SGT Flash memory cell can realize program and erase operation with a floating body structure.

Digital halftoning is a technique to convert a continuous-tone image into a binary image consisting of black and white dots. It is an important technique for printing machines and printers to output an image with few intensity levels or colors which looks similar to an input image. This paper surveys how algorithm engineering can contribute to digital halftoning or what combinatorial problems are related to digital halftoning. A common criterion on optimal digital halftoning leads to a negative result that obtaining an optimal halftoned image is NP-complete. So, there are two choices: approximation algorithm and polynomial-time algorithm with relaxed condition. Main algorithmic notions related are geometric discrepancy, matrix (or array) rounding problems, and network-flow algorithms.

This paper proposes a method to predict and control noise voltage caused by electrostatic discharge (ESD) to electronic equipment. The relationship of grounding system configurations for a typical set of equipment to ESD immunity has been derived using a mechanism of ground potential variations. The equivalent circuit representing ground elements as lumped constants enables us to predict the transient ground potential differences between PCB (Printed Circuit Board) ground planes connected via signal cables and induced noise voltage at the receiving end. The calculation shows that the contribution of ground potential differences to noise voltage is comparable to that of the electromagnetic coupling between the discharge current on the enclosure and the circuit loops. The calculation also shows some characteristic results, such as; the induced noise voltage is remarkably dependent on the unbalance in ground cable lengths and on the impedance of ground conductors connecting PCBs, especially when the equipment uses a single-point grounding system. These characteristics were confirmed by measurements of induced ground potential differences, noise voltage and immunity levels. Thus the proposed method is shown to be very effective to analyze the dependency of grounding conditions on ESD immunity and to improve ESD immunity in equipment design.

A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

It has become very important to study the lightning surges that flow into telecommunications equipment because of the increased use of circuits susceptible to excess voltage. This paper reports for the first time simultaneous measurements of distributed lightning current at many positions in a mountain-top radio relay station caused by natural direct lightning strikes. More than 90% of the direct lightning current flowed from the lightning rod to the ground through building structural components such as antenna tower legs, waveguides, and so on, with the high frequency components of the lightning current tending to flow into the outside parts of those structural components. And then, 25 to 43 % of the lightning current flowed out again to outside telecommunications cables and power lines because the lightning current raised the station's ground potential. Based on these measurements, to help predict lightning current which is dangerous to telecommunications equipment, lightning current occurrence probabilities at the waveguide and cables were estimated by analyzing the distribution ratios between the current in those components.