Internet behavior is becoming more complex due to ever-changing networking technologies and applications. Thus, understanding and controlling the complex behavior of the Internet are important for designing future networks. One of the complex behaviors of the Internet is traffic dynamics. Previous studies revealed that flow control in the transport layer affects the traffic dynamics of the Internet. However, it is not clear how the topological structure impacts traffic dynamics. In this paper, we investigate packet delay dynamics and traffic fluctuation in ISP router-level topologies where the degree distribution exhibits a power-law nature, and the nodes interact via end-to-end feedback control functionality. We show the packet delay dynamics of the BA topologies generated by the Barabasi-Albert (BA) model and the ISP router-level topologies. Simulation results show that the end-to-end delay distributions exhibit a heavy tail in the TCP model. Moreover, the number of links with highly fluctuating queue length increases dramatically compared to that in the stop-and-wait model. Even in this case, the high-modularity structures of the ISP topologies reduce the number of highly fluctuating links compared with the BA topologies.

This paper presents a single-cycle shared output buffered router for Networks-on-Chip. In output ports, each input port always has an output virtual-channel (VC) which can be exchanged by VC swapper. Its critical path is only 24 logic gates, and it reduces 9.4% area overhead compared with the classical router.

Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

As the Internet represents a key social infrastructure, its reliability is essential if we are to survive failures. Physical connectivity of networks is also essential as it characterizes reliability. There are collaboration structures, which are topological structures where two or more nodes are connected to a node, and collaboration structures are observed in transcriptional regulatory networks and the router-level topologies of ISPs. These collaboration structures are related to the reliability of networks. The main objective of this research is to find whether an increase in collaboration structures would improve reliability or not. We first categorize the topology into a three-level hierarchy for this purpose, i.e., top-level, middle-level, and bottom-level layers. We then calculate the reliability of networks. The results indicate that the reliability of most transcriptional regulatory networks is higher than that of one of router-level topologies. We then investigate the number of collaboration structures. It is apparent that there are much fewer collaboration structures between top-level nodes and middle-level nodes in router-level topologies. Finally, we confirm that the reliability of router-level topologies can be improved by rewiring to increase the collaboration structures between top-level and middle-level nodes.

In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 77 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.

The on-chip interconnection network (OCIN) is an integrated solution for system-on-chip (SoC) designs. The buffer architecture and size, however, dominate the performance of OCINs and affect the design of routers. This work analyzes different buffer architectures and uses a data-link two-level FIFO (first-in first-out) buffer architecture to implement high-performance routers. The concepts of shared buffers and multiple accesses for buffers are developed using the two-level FIFO buffer architecture. The proposed two-level FIFO buffer architecture increases the utilities of the storage elements via the centralized buffer organization and reduces the area and power consumption of routers to achieve the same performance achieved by other buffer architectures. Depending on a cycle-accurate simulator, the proposed data-link two-level FIFO buffer can realize performance similar to that of the conventional virtual channels, while using 25% of the buffers. Consequently, the two-level FIFO buffer can achieve about 22% power reduction compared with the similar performance of the conventional virtual channels using UMC 65 nm CMOS technology.

In existing systems of mobile routers, the frequency band is shared in uplinks from wireless terminals to mobile routers, and carrier sense multiple access with collision avoidance (CSMA/CA) is generally used as the medium access control protocol. To use the frequency band effectively, adaptive control is one promising approach. In this paper, a decentralized access control protocol in which mobile routers adaptively select the minimum contention window size is proposed. However, because of their mobility, which is one of the main difference between mobile routers and fixed access points, individual local area networks (LANs) consisting of the mobile routers and wireless terminals randomly interact with each other, and such random interactions can cause instability. To analyze the stability of the proposed control, evolutionary game theory is introduced because a system with random interactions between numerous decision-making entities can be analyzed by using evolutionary game theory. Using evolutionary game theory, the condition for existence of a convergence point is obtained. In addition, to implement the decentralized access control, a learning rule is proposed. In the proposed learning rule, each mobile router selects a strategy based on the result of past trials. From the simulation result, it is confirmed that the decentralized access control converges to a point closed to the stable state derived through evolutionary game theory.

Detecting distributed anomalies rapidly and accurately is critical for efficient backbone network management. In this letter, we propose a novel anomaly detection method that uses router connection relationships to detect distributed anomalies in the backbone Internet. The proposed method unveils the underlying relationships among abnormal traffic behavior through closed frequent graph mining, which makes the detection effective and scalable.

The Internet is an extremely convenient network and has become one of the key infrastructures for daily life. However, it suffers from three serious problems; its structure does not suit traffic centralization, its power consumption is rapidly increasing, and its round-trip time (RTT) and delay jitter are large. This paper proposes an extremely energy efficient layer-3 network architecture for the future Internet. It combines the Service Cloud with the Cloud Router and application servers, with the Optical Aggregation Network realized by optical circuit switches, wavelength-converters, and wavelength-multiplexers/demultiplexers. User IP packets are aggregated and transferred through the Optical Aggregation Network to Cloud transparently. The proposed network scheme realizes a network structure well suited to traffic centralization, reduces the power consumption to 1/20-1/30 compared to the existing Internet, reduces the RTT and delay jitter due to its simplicity, and offers easy migration from the existing Internet.

Selections of radio access networks by terminals are currently not coordinated and utilizations of the radio resources are not balanced. As a result, radio resources on some radio systems are occupied even though others can afford. In this paper, in order to provide a framework to resolve this issue, Cognitive Wireless Router (CWR) system is proposed for distributed management and independent reconfiguration of heterogeneous wireless networks. The proposed system selects appropriate operational frequency bands and radio systems to connect to the Internet in corporation between the CWRs and a server and therefore can provide optimized wireless Internet access easily even in environments without wired networks. The developed prototype system reconfigures the radio devices to connect to the Internet in 27 seconds at most. It is revealed that this reconfiguration time can be shortened to less than 100 ms by elaborating its procedure. It is also clarified that network data speed required at the server to deal with 10,000 CWRs is only 4.1 Mbps.

Ternary Content Addressable Memory (TCAM) is a special type of memory used in routers to achieve high-speed packet forwarding and classification. Packet forwarding is done by referring to the rules written in the routing table, whereas packet classification is performed by referring to the rules in the Access Control List (ACL). TCAM uses more transistors than Random Access Memory (RAM), resulting in high power consumption and high production cost. Therefore, it is necessary to reduce the entries written in the TCAM to reduce the transistor count. In this paper, we propose a new TCAM architecture by using Range Matching Devices (RMD) integrated within the TCAM's control logic with an optimized prefix expansion algorithm. The proposed method reduces the number of entries required to express ACL rules, especially when specifying port ranges. With less than 10 RMDs, the total number of lines required to write port ranges in the TCAM can be reduced to approximately 50%.

We present a congestion control algorithm for the Internet and assess its stability. The algorithm has low operation complexity and exercises control over sources without keeping per-flow information. Given the lack of support for explicit-rate feedback in the Internet, we discuss an implementation where feedback is based on explicit binary indications. We assess the stability through a discrete-time model and present simulation results showing the efficacy of the algorithm. The obtained results indicate that when the algorithm is used to control sources that support explicit binary feedback, its stability is not affected and its performance is close to that obtained with sources that support explicit-rate feedback.

We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40 GHz for an automatically routed 44 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.

Multimedia traffic on the Internet is rapidly increasing with the advent of broadband networks. However, the Best-Effort (BE) service used with Internet Protocol (IP) networking was never intended to guarantee Quality of Service (QoS) for each user. Therefore, the realization of QoS guarantees has become a very important issue. Previously, we have proposed a queue management scheme, called Dual Metrics Fair Queuing (DMFQ), to improve fairness and to guarantee QoS. DMFQ improves fairness and throughput by considering the amount of instantaneous and historical network resources consumed per flow. In addition, DMFQ has characteristics of high speed and high scalability because it is hardware oriented. However, DMFQ may be unable to adapt to network fluctuations, given that it has static setup parameters. Moreover, DMFQ is unable to support a multiclass environment. In this paper, we propose a new buffer management scheme based on DMFQ that can adapt flexibly to network conditions and can provide classified services. The proposed scheme stabilizes buffer utilization within a fixed range by controlling the buffer threshold, which affects the calculated packet discard probability. Moreover, by applying the proposed scheme to Differentiated Services (DiffServ), we achieve prioritized buffer management.

Internet routers need to classify incoming packets quickly into flows in order to support features such as Internet security, virtual private networks and Quality of Service (QoS). Packet classification uses information contained in the packet header, and a predefined rule table in the routers. Packet classification of multiple fields is generally a difficult problem. Hence, researchers have proposed various algorithms. This study proposes a multi-dimensional encoding method in which parameters such as the source IP address, destination IP address, source port, destination port and protocol type are placed in a multi-dimensional space. Similar to the previously best known algorithm, i.e., bitmap intersection, multi-dimensional encoding is based on the multi-dimensional range lookup approach, in which rules are divided into several multi-dimensional collision-free rule sets. These sets are then used to form the new coding vector to replace the bit vector of the bitmap intersection algorithm. The average memory storage of this encoding is θ (LNlog N) for each dimension, where L denotes the number of collision-free rule sets, and N represents the number of rules. The multi-dimensional encoding practically requires much less memory than bitmap intersection algorithm. Additionally, the computation needed for this encoding is as simple as bitmap intersection algorithm. The low memory requirement of the proposed scheme means that it not only decreases the cost of packet classification engine, but also increases the classification performance, since memory represents the performance bottleneck in the packet classification engine implementation using a network processor.

The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

To guarantee strict Quality of Service (QoS) for real-time applications, we have previously proposed an output buffer control mechanism in IP routers, confirmed its effectiveness through simulations, and implemented a prototype. This mechanism can guarantee strict QoS within a single router. In this paper, we propose a control scheme of cooperation between IP routers equipped with this mechanism by using one of the signaling protocols. Our proposed scheme aims to stabilize End-to-End (E2E) flow delay within the target delay. In addition, our mechanism dynamically updates reserved resources between IP routers to improve E2E packet loss rate. We present an implemented design of our scheme and an empirical evaluation of the implementation. These results show quantitatively how our scheme improves the quality of video pictures.

A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology including two-surface layout, it does not affect the design of the other layer, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the none temporal correlation algorithm suffers from 30% performance loss.

The effect of inconsistencies in forwarding tables on the reachability of IP packets is evaluated. To improve a router's availability, in the architecture of current routers, the control element is separated from the forwarding element. However, a router with the current architecture cannot handle a notification for which the topology of the network system changes when its control element has stopped. In such a case, the router cannot update its own forwarding table, and an inconsistency between the forwarding tables of the router and those of the other routers will occur. To investigate the influence of this inconsistency, we formalize the network system, and derive the conditions under which such an inconsistency leads to unreachable routes. After that, the number of routes that are unreachable is evaluated by simulations. These simulations show that routing loops occur more frequently under the condition that a failed node is close to the restarting node or fewer links exist in the network system.

IP (Intellectual Property) reuse plays an important role in modern IC design so that IP Protection (IPP) technique is get concerned. In this paper, we introduce a new efficient watermarking system for IPP on post-layout design stage. The signature (which indicates the designer) is encrypted with a secret key by DES (Data Encryption Standard) to produce a bit string, which is then embedded into the layout design as constraints by using a specific incremental router. Once the design is watermarked successfully, the signature can be extracted accurately by the system. The system also has a strong resistance to the attack on watermarking due to the DES functionality. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without our tool. We evaluated the watermarking system on IBM-PLACE 2.0 benchmark suites. The results show the system robustness and strength: the system success probability achieves 100% in suitable time with no extra area and wire length cost on design performances.