The theoretically minimum length of a signal for fundamental frequency estimation in a noisy environment is discussed. Assuming that the noise is additive white Gaussian, it is known that a Cramér-Rao lower bound (CRLB) is given by the length and other parameters of the signal. In this paper, we define the minimum length as the length whose CRLB is less than or equal to the specific variance for any parameters of the signal. The specific variance is allowable variance of the estimate within an application of fundamental frequency estimation. By reformulating the CRLB with respect to the initial phase of the signal, the algorithms for determining the minimum length are proposed. In addition, we develop the methods of deciding the specific variance for general fundamental frequency estimation and pitch estimation. Simulation results in terms of both the fundamental frequency estimation and the pitch estimation show the validity of our approach.

We propose a novel algorithm for the recovery of non-sparse, but compressible signals from linear undersampled measurements. The algorithm proposed in this paper consists of two steps. The first step recovers the signal by the l1-norm minimization. Then, the second step decomposes the l1 reconstruction into major and minor components. By using the major components, measurements for the minor components of the target signal are estimated. The minor components are further estimated using the estimated measurements exploiting a maximum a posterior (MAP) estimation, which leads to a ridge regression with the regularization parameter determined using the error bound for the estimated measurements. After a slight modification to the major components, the final estimate is obtained by combining the two estimates. Computational cost of the proposed algorithm is mostly the same as the l1-nom minimization. Simulation results for one-dimensional computer generated signals show that the proposed algorithm gives 11.8% better results on average than the l1-norm minimization and the lasso estimator. Simulations using standard images also show that the proposed algorithm outperforms those conventional methods.

We investigate a quantization error improvement technique using a dual rail configuration for optical quantization. Our proposed optical quantization uses intensity-to-wavelength conversion based on soliton self-frequency shift and spectral compression based on self-phase modulation. However, some unfavorable input peak power regions exist due to stagnations of wavelength shift or distortions of spectral compression. These phenomena could induce a serious quantization error and degrade the effective number of bit (ENOB). In this work, we propose a quantization error improvement technique which can make up for the unfavorable input peak power regions. We experimentally verify the quantization error improvement effect by the proposed technique in 6 bit optical quantization. The estimated ENOB is improved from 5.35 bit to 5.66 bit. In addition, we examine the XPM influence between counter-propagating pulses at high sampling rate. Experimental results and numerical simulation show that the XPM influence is negligible under ∼40 GS/s conditions.

Track mis-registration (TMR) is one of the major problems in high-density magnetic recording systems such as bit-patterned media recording (BPMR). In general, TMR results from the misalignment between the center of the read head and that of the main track, which can deteriorate the system performance. Although TMR can be handled by a servo system, this paper proposes a novel method to alleviate the TMR effect, based on the readback signal. Specifically, the readback signal is directly used to estimate a TMR level and is then further processed by the suitable target and equalizer designed for such a TMR level. Simulation results indicate that the proposed method can sufficiently estimate the TMR level and then helps improve the system performance if compared to the conventional receiver that does not employ a TMR mitigation method, especially when an areal density is high and/or a TMR level is large.

Studies on gaze analysis have revealed some of the relationships between viewers' gaze and their internal states (e.g., interests and intentions). However, understanding content browsing behavior in uncontrolled environments is still challenging because human gaze can be very complex; it is affected not only by viewers' states but also by the spatio-semantic structures of visual content. This study proposes a novel gaze analysis framework which introduces the content creators' point of view to understand the meaning of browsing behavior. Visual content such as web pages, digital articles and catalogs are comprised of structures intentionally designed by content creators, which we refer to as designed structure. This paper focuses on two design factors of designed structure: spatial structure of content elements (content layout), and their relationships such as “being in the same group”. The framework was evaluated with an experiment involving 12 participants, wherein the participant's state was estimated from their gaze behavior. The results from the experiment show that the use of design structure improved estimation accuracies of user states compared to other baseline methods.

The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.

All-optical 1-to-6 wavelength multicasting of a 10-Gb/s picosecond-tunable-width converted return-to-zero (RZ)-on-off-keying (OOK) data signal using a wideband-parametric pulse source from a distributed Raman amplifier (DRA) is experimentally demonstrated. Width-tunable wavelength multicasting within the C-band with approximately 40.6-nm of separation with various compressed RZ data signal inputs have been proposed and demonstrated. The converted multicast pulse widths can be flexibly controlled down to 2.67 ps by tuning the Raman pump powers of the DRA. Nearly equal pulse widths at all multicast wavelengths are obtained. Furthermore, wide open eye patterns and penalties less than 1.2 dB at the 10-9 bit-error-rate (BER) level are found.

We demonstrated that load balancing using actual subscriber extension numbers was practical and effective against traffic congestion after a disaster based on actual data. We investigated the ratios of the same subscriber extension numbers in each prefecture and found that most of them were located almost evenly all over the country without being concentrated in a particular area. The ratio of every number except for the fourth-last digit in the last group of four numbers in a telephone number was used almost equally and located almost evenly all over the country. Tolerance against overload in the last, second-, and third-last single digits stays close to that in the ideal situation if we assume that each session initiation protocol server has a capacity in accordance with the ratio of each number on every single digit in the last group of four numbers in Japan. Although tolerance against overload in double-, triple-, and quadruple-digit numbers does not stay close to that in the ideal situation, it still remains sufficiently high in the case of double- and triple-digit numbers. Although tolerance against overload in the quadruple-digit numbers becomes low, disaster congestion is still not likely to occur in almost half of the area of Japan (23 out of 47 prefectures).

In this paper, a threshold-based I-Q diversity combining scheme for ultra-high frequency (UHF) radio frequency identification (RFID) readers with a quadrature receiver is proposed in the aspect of improving the tag detection performance. In addition, the performance of the proposed scheme is evaluated as the closed-form expressions. In particular, its statistical characteristics are detailed and its performance is compared to that of conventional schemes over independent and identically distributed Rician fading conditions in terms of average signal-to-noise ratio (SNR), bit error rate (BER), and the average number of required combining process. Numerical results indicate that the proposed scheme enables processing power control through threshold control while meeting the required quality of service compared to conventional schemes.

A combination of nonreturn-to-zero (NRZ)-to-return-to-zero (RZ) waveform conversion and wavelength multicasting with pulsewidth tunability is experimentally demonstrated. A NRZ data signal is injected into a highly nonlinear fiber (HNLF)-based four-wave mixing (FWM) switch with four RZ clocks compressed by a Raman amplification-based multiwavelength pulse compressor (RA-MPC). The NRZ signal is multicast and converted to RZ signals in a continuously wide pulsewidth tuning range between around 12.17 and 4.68 ps by changing the Raman pump power of the RA-MPC. Error-free operations of the converted RZ signals with different pulsewidths are achieved with negative power penalties compared with the back-to-back NRZ signal and the small variation among received powers of RZ output channels at a bit-error-rate (BER) of 10-9. The NRZ-to-RZ waveform conversion and wavelength multicasting without using the RA-MPC are also successfully implemented.

Passive SONAR receives a mixed form of signal that is a combination of continuous and discrete line-component spectrum signals. The conventional algorithms, DEMON and LOFAR, respectively target each type of signal, but do not consider the other type of signal also present in the practical environment. Thus when features from two types of signals are presented at the same time, analysis results may cause confusion. In this paper, we propose an integrated analysis algorithm for underwater signals using the modulation spectrogram domain. The proposed domain presents the visual difference between the different types of signal, and therefore can prevent confusion that would otherwise be feasible. Moreover, the proposed algorithm is more efficient than multiband DEMON in terms of computation complexity, while in colored ambient noise environment, it has similar performance to conventional DEMON and LOFAR. We prove the validity of the proposed algorithm through the relevant experiments with synthesized signal and actual underwater recordings.

As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring the middle points, or check points of several speed-paths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

RXv2 is the new generation of Renesas's processor architecture for microcontrollers with high-capacity flash memory. An enhanced instruction set and pipeline structure with an advanced fetch unit (AFU) provide an effective balance between power consumption performance and high processing performance. Enhanced instructions such as DSP function and floating point operation and a five-stage dual-issue pipeline synergistically boost the performance of digital signal applications. The RXv2 processor delivers 1.9 - 3.7 the cycle performance of the RXv1 in these applications. The decrease of the number of Flash memory accesses by AFU is a dominant determiner of reducing power consumption. AFU of RXv2 benefits from adopting branch target cache, which has a comparatively smaller area than that of typical cache systems. High code density delivers low power consumption by reducing instruction memory bandwidth. The implementation of RXv2 delivers up to 46% reduction in static code size, up to 30% reduction in dynamic code size relative to RISC architectures. RXv2 reaches 4.0 Coremark per MHz and operates up to 240MHz. The RXv2 processor delivers approximately more than 2.2 - 5.7x the power efficiency of the RXv1. The RXv2 microprocessor achieves the best possible computing performance in various applications such as building automation, medical, motor control, e-metering, and home appliances which lead to the higher memory capacity, frequency and processing performance.

In this paper, a new parameter estimator for coherently distributed (CD) noncircular (NC) signals is proposed, and can estimate both the central direction-of-arrivals (DOAs) and the angular spreads. It can also be considered as an extended version of the generalized Capon method by using both covariance matrix and an elliptic covariance matrix. The central DOAs and angular spreads are obtained by two-dimensional spectrum-peak searching. Numerical examples illustrate that the proposed method can estimate the central DOAs and the angular spreads when the number of signals is greater than the number of sensors. The proposed method also offers better performance than the methods against which it is compared.

We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64dB is achievable at an input signal frequency of 10kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.

In this paper the amplitude probability distribution (APD) measurement method is applied to evaluate noise coupling to an antenna on an evaluation board that uses mixed RF and digital signals of an IC. We analytically investigate noise coupling path to the antenna where the correlation coefficient matches the APD curve of the evaluation board. Moreover, in order to verify the analysis results, the noise coupling path in the board is evaluated by measurements involving In-phase/Quadrature (I/Q) signals as well as electromagnetic simulations. As a result, we demonstrate that APD method is effective in evaluating a degree of noise coupling from an IC to multiple antennas on the board, and confirm that the intensity of noise coupling to each antenna is affected greatly by the board layout patterns.

A 32bit CPU, which can operate more than 15 years with 220mAH Li battery, or eternally operate with an energy harvester of in-door light is presented. The CPU was fabricated by using 65nm SOTB CMOS technology (Silicon on Thin Buried oxide) where gate length is 60nm and BOX layer thickness is 10nm. The threshold voltage was designed to be as low as 0.19V so that the CPU operates at over threshold region, even at lower supply voltages down to 0.22V. Large reverse body bias up to -2.5V can be applied to bodies of SOTB devices without increasing gate induced drain leak current to reduce the sleep current of the CPU. It operated at 14MHz and 0.35V with the lowest energy of 13.4 pJ/cycle. The sleep current of 0.14µA at 0.35V with the body bias voltage of -2.5V was obtained. These characteristics are suitable for such new applications as energy harvesting sensor network systems, and long lasting wearable computers.

Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.

This paper proposes a novel greedy algorithm, called Creditability-Estimation based Matching Pursuit (CEMP), for the compressed sensing signal recovery. As proved in the algorithm of Stagewise Orthogonal Matching Pursuit (StOMP), two Gaussian distributions are followed by the matched filter coefficients corresponding to and without corresponding to the actual support set of the original sparse signal, respectively. Therefore, the selection for each support point is interpreted as a process of hypothesis testing, and the preliminarily selected support set is supposed to consist of rejected atoms. A hard threshold, which is controlled by an input parameter, is used to implement the rejection. Because the Type I error may happen during the hypothesis testing, not all the rejected atoms are creditable to be the true support points. The creditability of each preliminarily selected support point is evaluated by a well-designed built-in mechanism, and the several most creditable ones are adaptively selected into the final support set without being controlled by any extra external parameters. Moreover, the proposed CEMP does not necessitate the sparsity level to be a priori control parameter in operation. In order to verify the performance of the proposed algorithm, Gaussian and Pulse Amplitude Modulation sparse signals are measured in the noiseless and noisy cases, and the experiments of the compressed sensing signal recoveries by several greedy algorithms including CEMP are implemented. The simulation results show the proposed CEMP can achieve the best performances of the recovery accuracy and robustness as a whole. Besides, the experiment of the compressed sensing image recovery shows that CEMP can recover the image with the highest Peak Signal to Noise Ratio (PSNR) and the best visual quality.

Verification of a design with respect to its requirement specification is important to prevent errors before constructing an actual implementation. The existing works focus on verifications where the specifications are described using temporal logics or using the same languages as that used to describe the designs. Our work considers cases where the specifications and the designs are described using different languages. To verify such cases, we propose a framework to check if a design conforms to its specification based on their simulation relation. Specifically, we define the semantics of the specifications and the designs commonly as labelled transition systems (LTSs). We appreciate LTSs since they could interpret information about the system and actions that the system may perform as well as the effect of these actions. Then, we check whether a design conforms to its specification based on the simulation relation of their LTS. In this paper, we present our framework for the verification of reactive systems, and we present the case where the specifications and the designs are described in Event-B and Promela/Spin, respectively. We also present two case studies with the results of several experiments to illustrate the applicability of our framework on practical systems.