We report a 40-Gb/s and highly accurate intensity limiter with a single Erbium-Doped Fiber Amplifier (EDFA) for low-power-consumption driving intensity limiting. The intensity limiter based on self-phase modulation with an appropriate pre-chirping procedure makes it possible, which provides a highly accurate limiting of less than 0.01 dB. We fed 40-Gb/s signals with 2.69 dB intensity fluctuation and 4.7 dB improvement on the receiver sensitivity was obtained for a bit error rate of 10-9 by using a numerical simulation.

This paper presents an efficient approach for logarithmic and anti-logarithmic converters which can be used in the arithmetic unit of hybrid number system processors and logarithm/exponent function generators in DSP applications. By employing the novel quasi-symmetrical difference method with only the simple shift-add logic and the look-up table, the proposed approach can reduce the hardware area and improve the conversion speed significantly while achieve similar accuracy compared with the previous methods. The implementation results in both FPGA and 0.18-µm CMOS technology are also presented and discussed.

This paper presents analysis and design of passive RC polyphase filters (RCPFs) in tutorial style. Single-phase model of a single-stage RCPF is derived, and then, multi-stage RCPFs are analyzed and obtained some restrictions for realizable poles and zeros locations of RCPFs. Exact design methods of RCPFs with equal ripple type, and Butterworth type responses are explained for transfer function design and element value design along with some design examples.

This paper presents an architecture of signal-dependent analog-to-digital converter (ADC) based on MINIMAX sampling scheme that allows achieving high data compression rate and power reduction. The proposed architecture consists of a conventional synchronous ADC, a timer and a peak detector. AD conversion is carried out only when input signal peaks are detected. To improve the accuracy of signal reconstruction, MINIMAX sampling is improved so that multiple points are captured for each peak, and its effectiveness is experimentally confirmed. In addition, power reduction, which is the primary advantage of the proposed signal-dependent ADC, is analytically discussed and then validated with circuit simulations.

In this letter, we point out that key substitution attacks should be taken into account for multisignature schemes, which implies that the existing security notions for multisignature schemes are not sufficient. As an example, we show that the multisignature scheme proposed by Boldyreva at PKC'03 is susceptible to key substitution attacks.

In this paper, a new bandwidth allocation scheme is proposed based on the Mechanism Design (MD); MD is a branch of game theory that stimulates rational users to behave cooperatively for a global goal. The proposed scheme consists of bandwidth adaptation, call admission control and pricing computation algorithms to improve network performance. These algorithms are designed based on the adaptive online approach and work together to maximize bandwidth efficiency economically. A simulation shows that the proposed scheme can satisfy contradictory requirements and so provide well-balanced network performance.

The conventional Equal Gain Transmission and Maximum Ratio Combining (EGT/MRC) requires nonlinear optimization to find the optimal beamforming vector at the receiver. This study shows that the optimal beamforming vector can be easily formed by the geometrical concepts. Accordingly, a novel transmission/reception scheme, called the Scalar Equal Gain Transmission and Generalized Maximum Ratio Combining (SEGT/GMRC), is presented and examined. The Monte-Carlo simulations validate the theory and it is shown that the optimal beamforming vector formed by SEGT is the same as the one determined by the nonlinear optimizer. The closed-form analytical error performance of the SEGT/GMRC scheme is also derived for multiple input single output (MISO) communications. This study also introduces the new limited-feedback geometrical codebooks, called the Quantized Equal gain (QE) codebooks, which can be easily installed as symbol mappers. These codebooks are based on quantized SEGT/GMRC, which eliminates the need for any iterative searching scheme, such as exhaustive search at the receiver. The minimum amount of feedback bits depends on the modulation scheme, where a general M-PSK modulation requires at least log2M bits per quantized phase angle. It is also shown that BPSK modulation requires at least 2 bits per quantized phase angle for near-optimal performance.

At Eurocrypt'2006, Lu et al. proposed a pairing based verifiably encrypted signature scheme (the LOSSW-VES scheme) without random oracles. In this letter, we show that the LOSSW-VES scheme does not have opacity against rogue-key attacks.

This paper presents a high-efficiency boost converter with voltage clamp function. It clarifies how to design the inductance of the coupled inductor used in the converter, and derives characteristic equations that associate the fluctuation in the input voltage with the output ripple current. For this converter, a theoretical analysis, simulation and experimentation (prototype output: 98 V, 13 A) are performed. As a result, the converter is achieved high efficiency (Maximum efficiency: 98.1%) in the rated output condition, indicating that the voltage stress on the switching power semiconductors can be mitigated by using the voltage clamp function. And it is verified that the snubber circuit can be eliminated in the switching power semiconductors. In addition, the theoretical output ripple current characteristics are corresponded well with simulation and experimental results, and the validity of the design method is proved.

In this paper, we present a framework to construct message recovery signature schemes from Sigma-protocols. The key technique of our construction is the redundancy function that adds some redundancy to the message only legitimately signed and recovered message can have. We provide a characterization of the redundancy functions that make the resulting message recovery signature scheme proven secure. Our framework includes known schemes when the building blocks are given concrete implementations, i.e., random oracles and ideal ciphers, hence presents insightful explanation to their structure.

This letter describes the design methodology for reduced reconfigurable logic circuits based on double gate carbon nanotube field effect transistors (DG-CNTFETs) with ambipolar propoerty. Ambipolar Binary Decision Diagram (Am-BDD) which represents the cornerstone for automatic pass transistor logic (PTL) synthesis flows of ambipolar devices was utilized to build DG-CNTFET based n-input reconfigurable cells in the conventional approach. The proposed method can reduce the number of ambipolar devices for 2-inputs reconfigurable cells, incorporating the simple Boolean algebra in the Am-BDD compared with the conventional approach. As a result, the static 2-inputs reconfigurable circuit with 16 logic functions can be synthesized by using 8 DG-CNTFETs although the previous design method needed 12 DG-CNTFETs for the same purpose.

Product return is a critical but controversial issue. To deal with such a vague return problem, businesses must improve their information transparency in order to administrate the product return behaviour of their end users. This study proposes an intelligent return administration expert system (iRAES) to provide product return forecasting and decision support for returned product administration. The iRAES consists of two intelligent agents that adopt a hybrid data mining algorithm. The return diagnosis agent generates different alarms for certain types of product return, based on forecasts of the return possibility. The return recommender agent is implemented on the basis of case-based reasoning, and provides the return centre clerk with a recommendation for returned product administration. We present a 3C-iShop scenario to demonstrate the feasibility and efficiency of the iRAES architecture. Our experiments identify a particularly interesting return, for which iRAES generates a recommendation for returned product administration. On average, iRAES decreases the effort required to generate a recommendation by 70% compared to previous return administration systems, and improves performance via return decision support by 37%. iRAES is designed to accelerate product return administration, and improve the performance of product return knowledge management.

MPEG spatial audio object coding (SAOC) is a new audio coding standard which efficiently represents various audio objects as a down-mix signal and spatial parameters. MPEG SAOC has a backward compatibility with existing playback systems for the down-mix signal. If a mastering signal is used for providing CD-like sound quality instead of the down-mix signal, an output signal decoded with the mastering signal may be easily degraded due to the difference between the down-mix and the mastering signals. To successfully use the mastering signal in MPEG SAOC, the difference between two signals should be eliminated. As a simple mastering signal processing, we propose a mastering signal processing using the mastering down-mix gain (MDG) which is similar to the arbitrary down-mix gain of MPEG Surround. Also, we propose an enhanced mastering signal processing using the MDG bias in order to reduce quantization errors of the MDG. Experimental results show that the proposed schemes can improve sound quality of the output signal decoded with the mastering signal. Especially, the enhanced method shows better performance than the simple method in the aspects of the quantization errors and the sound quality.

Based on a proposed frame structure with an unequal sensing slot duration for each channel, and two sensing scenarios (with or without cooperation), a joint channel and sensing time assignment is suggested to maximize the uplink throughput of the centralized multi-band cognitive radio network with the consideration of the mutual interference among the secondary users (SUs). Firstly, the channel assignment is performed by using the proposed Delta Non-square Hungarian (DNH), which is a modified iterative Hungarian algorithm distinguished by throughput increment maximization and non-square weight matrix. Simulation results illustrate that DNH has significant advantages in enhancing the throughput and reducing the computational complexity. Moreover, a hybrid channel assignment, also performed by DNH, is improved based on the two sensing scenarios to maximize the throughput while efficiently limiting the interference power to primary users. Secondly, the convexity of the throughput functions within the range of sensing time is proved under the proposed frame structure, and then the maximum throughput is achieved through the steepest descent method-based sensing time assignment. Both of these results are corroborated by simulations.

We propose optical path routing and frequency slot assignment algorithms that can make the best use of elastic optical paths and the capabilities of distance adaptive modulation. Due to the computational difficulty of the assignment problem, we develop algorithms for 1+1 dedicated/1:1 shared protected ring networks and unprotected mesh networks to that fully utilize the characteristics of the topologies. Numerical experiments elucidate that the introduction of path elasticity and distance adaptive modulation significantly reduce the occupied bandwidth.

An analytical performance evaluation model is presented in this paper. A time-splitting transmitter circuit employing a selectively activated flip-driver (SAFD) is presented and its performance is estimated by the new model. The optimal partitioning method which maximizes the performance of a given bus-invert (BI) coding circuit is also presented. When a bus is optimally partitioned, an ordinary BI circuit can reduce the number of bus transitions by about 25%, while an SAFD circuit can remove about 35% of them. The newly developed method is verified by simulations whose results correspond very well to the values predicted by the model.

Dual-vdd has been proposed to optimize the power of circuits without violating the performance. In this paper, different from traditional methods which focus on making full use of slacks of non-critical gates, an efficient min-cut based voltage assignment algorithm concentrating on critical gates is proposed. And then this algorithm is integrated into a searching engine to auto-select rational voltages for dual-vdd system. Experimental results show that our search engine can always achieve good pair of dual-vdd, and our min-cut based algorithm outperformed previous works for voltage assignment both on power consumption and runtime.

Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).

In this letter, we propose a fast dynamic slot assignment (F-DSA) protocol to reduce timeslot access delay of a newly arrived node in ad hoc networks. As there is no central coordinator, a newly arrived node needs separate negotiation with all the neighboring nodes for assigning slots to itself. Thus, it may result in network join delay and this becomes an obstacle for nodes to dynamically join and leave networks. In order to deal with this issue better, F-DSA simplifies the slot assignment process. It provides frequent opportunities to assign slots by using mini-slots to share control packets in a short time. Numerical analysis and extensive simulation show that F-DSA can significantly reduce the timeslot access delay compared with other existing slot assignment protocols. In addition, we investigate the effect of the mini-slot overhead on the performance.

This study examines the robustness of image quality factors in various types of environment illumination using a parameter design in the field of quality engineering. Experimental results revealed that image quality factors are influenced by environment illuminations in the following order: minimum luminance, maximum luminance and gamma.