Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined.

Dependence of within-die delay variations on power supply voltage (VDD) is measured down to 0.4 V. The VDD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing VDD from 1.2 V to 0.4 V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD.

In an undirected graph, the feedback vertex set (FVS for short) problem is to find a set of vertices of minimum cardinality whose removal makes the graph acyclic. The FVS has applications to several areas such that combinatorial circuit design, synchronous systems, computer systems, VLSI circuits and so on. The FVS problem is known to be NP-hard on general graphs but interesting polynomial solutions have been found for some special classes of graphs. In this paper, we present an O(n2.68 + γn) time algorithm for solving the FVS problem on trapezoid graphs, where γ is the total number of factors included in all maximal cliques.

We propose a new resource prediction method for the Demand Assigned Multiple Access (DAMA) scheme in satellite networks. Inaccurate prediction of future traffic causes degradation of QoS and utilization due to the long delay in satellite networks. The Dynamic Leveling Scheme (DLS) use a leveling method to modify its prediction to a discrete one to change the precision of the prediction result. This new scheme has two features: 1) It enhances the probability of successful prediction and 2) it can be applied to any type of existing prediction method. Simulations show enhanced utilization and performance of the satellite link.

This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

It is well known that the problem to solve a set of randomly chosen multivariate quadratic equations over a finite field is NP-hard. However, when the number of variables is much larger than the number of equations, it is not necessarily difficult to solve equations. In fact, when n ≥ m(m+1) (n,m are the numbers of variables and equations respectively) and the field is of even characteristic, there is an algorithm to find one of solutions of equations in polynomial time (see [Kipnis et al., Eurocrypt '99] and also [Courtois et al., PKC '02]). In the present paper, we propose two new algorithms to find one of solutions of quadratic equations; one is for the case of n ≥ (about) m2-2m 3/2+2m and the other is for the case of n ≥ m(m+1)/2+1. The first one finds one of solutions of equations over any finite field in polynomial time, and the second does with O(2m) or O(3m) operations. As an application, we also propose an attack to UOV with the parameters given in 2003.

In this paper, we compare 1/f noise characteristics of High-k/Metal Gate MOSFET and SiON/Poly-Si Gate MOSFET experimentally, and evaluate the time fluctuation of drive current. These MOSFETs are fabricated with 65 nm CMOS process, and their gate lengths (Lg) are 130 nm. Specifically, we focus on the dependency of the time fluctuation of drive current on channel width (W) and temperature (T). First, we evaluate the dependency on channel width. In the case of SiON/Poly-Si Gate MOSFET, when the channel width is narrow such as W=200 nm and W=250 nm, Power Spectrum Density (PSD) depends on 1/f2 at two frequency regions. Moreover, as the channel width is wide such as W=300 nm, W=500 nm and W=1000 nm, PSD depends on 1/f and the value of PSD shifts lower. This is a new phenomena observed for the first time. On the other hand, in the case of High-k/Metal Gate MOSFET, the value of PSD is about 100 times larger than that of SiON/Poly-Si Gate MOSFET. Moreover, there is no dependency of PSD on channel width ranges from 150 nm to 1000 nm. Second, we evaluate the dependency on temperature. In the case of SiON/Poly-Si Gate MOSFET, when the temperature (T) is lowered from T=27 to T=-35, the dependency changes from the 1/f dependency to the 1/f2 dependency at two different frequency regions. This is also a new phenomena observed for the first time. However, in the case of High-k/Metal Gate MOSFET, there is no dependency of PSD on temperature ranges from 27 to -35. These results are useful knowledge for designing future LSI, because PSD dependency shows different characteristics when both channel width and temperature are changed.

We present a design optimization method of H-plane waveguide components, based on the level set method with the finite element method. In this paper, we propose a new formulation for the improvement of a level set function, which describes shape, location, and connectivity of dielectric in a design region. Employing the optimization procedure, we demonstrate that optimized structures of an H-plane waveguide filter and T-junction are obtained from an initial structure composed of several circular blocks of dielectric.

In this paper, a soft-error-tolerant BILBO (Built-In Logic Block Observer) FF (flip-flop) is presented. The proposed FF works as a soft-error-tolerant FF in system operations and as a BILBO FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft-error-tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft-error-tolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. The evaluation results shown in this paper indicate that the area of the proposed FF is 8.5% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 19.7% shorter than that for the combination.

This paper reports the DC and RF characteristics of AlN/GaN MOS-HEMTs passivated with thin Al2O3 formed by thermal oxidation of evaporated aluminium. Extraction of the small-signal equivalent circuit is also described. Device fabrication involved wet etching of evaporated Al from the Ohmic contact regions prior to metal deposition. This approach yielded an average contact resistance of ∼0.76 Ω.mm extracted from transmission line method (TLM) characterisation. Fabricated two-finger AlN/GaN MOS-HEMTs with 0.2 µm gate length and 100 µm gate width showed good gate control of drain currents up to a gate bias of 3 V and achieved a maximum drain current, IDSmax of ∼1460 mA/mm. The peak extrinsic transconductance, Gmax, of the device was ∼303 mS/mm at VDS = 4 V. Current-gain cut-off frequency, fT, and maximum oscillation frequency, fMAX, of 50 GHz and 40 GHz, respectively, were extracted from S-parameter measurements. For longer gate length, LG = 0.5 µm, fT and fMAX were 20 GHz and 30 GHz, respectively. These results demonstrate the potential of AlN/GaN MOS-HEMTs for high power and high frequency applications.

This paper presents a Multiple-Input Multiple-Output (MIMO) propagation model for independent and identically distributed (i.i.d.) channels in the mixture of none-Line-of-Sight (NLOS) and Line-of-Sight (LOS) environments. The derived model enables to evaluate the system statistical characteristics of Signal-to-Noise-Ratio (SNR) for MIMO transmission based on Maximal Ratio Combing (MRC). An application example applying the model in 22 configuration to ITS Inter-Vehicle Communication (IVC) system is introduced. We clarify the effectiveness of the proposed model by comparisons of both computer simulations and measurement results of a field experiment. We also use the model to show the better performance of SNR when applying MIMO to IVC system than SISO and SIMO.

Recently, assuming ideal brick-wall transmit filtering, we proposed a frequency-domain block signal detection (FDBD) with maximum likelihood detection employing QR decomposition and M-algorithm (called QRM-MLD) for the reception of single-carrier (SC) signals transmitted over a frequency-selective fading channel. QR decomposition (QRD) is applied to a concatenation of the propagation channel and discrete Fourier transform (DFT). However, a large number of surviving paths is required in the M-algorithm to achieve sufficiently improved bit error rate (BER) performance. The introduction of filtering can achieve improved BER performance due to larger frequency diversity gain while keeping a lower peak-to-average power ratio (PAPR) than orthogonal frequency division multiplexing (OFDM). In this paper, we develop FDBD with QRM-MLD for filtered SC signal reception. QRD is applied to a concatenation of transmit filter, propagation channel, and DFT. We evaluate BER and throughput performances by computer simulation. From performance evaluation, we discuss how the filter roll-off factor affects the achievable BER and throughput performances and show that as the filter roll-off factor increases, the required number of surviving paths in the M-algorithm can be reduced.

Hop-timing detection is of extreme importance for the reception of frequency hopping (FH) signals. Any error in the hop-timing detection has a deleterious effect on the performance of the receiver in frequency hopping (FH) communication systems. However, it is not easy to detect the hop-timing under low signal to noise power ratio (SNR) environments. Adaptive array antennas (AAA) have been expected to improve the performance of FH communication systems by beamforming for the direction of arrival of the desired signal. Since the conventional AAA exploits at least the coarse synchronization for dehopping of FH signals before achieving the beamforming, any fault in the hop-timing detection causes the deterioration of the performance of AAA. Using AAA based on the constant modulus algorithm (CMA), this paper proposes a new method for blind beamforming and hop-timing detection for FH signals. The proposed method exploits both the spatial and temporal characteristics of the received signal to accomplish the beamforming and detect the hop-timing without knowing any a priori information such as fine/coarse time synchronization and training signal. The performance verifications of the proposed method based on pertinent simulations are presented.

Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become a matter of concern as integrated circuits continue to shrink. It is getting more and more important to take reliability requirements into account even for consumer products. This paper presents a dynamic continuous signature monitoring (DCSM) technique for high reliable computer systems. The DCSM technique dynamically generates reference signatures as well as runtime ones during executing a program. The DCSM technique stores the generated signatures in a signature table, which is a small storage circuit in a microprocessor, unlike the conventional static continuous signature monitoring techniques and contributes to saving program or data memory space that stores the signatures. Our experiments showed that our DCSM technique protected 1.4-100.0% of executed instructions depending on the size of signature tables.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [1] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.

This paper presents a single-chip RF tuner/OFDM demodulator for a mobile digital TV application called “1-segment broadcasting.” To achieve required performances for the single-chip receiver, a tunable technique for a low-noise amplifier (LNA) and spurious suppression techniques are proposed in this paper. Firstly, to receive all channels from 470 MHz to 770 MHz and to relax distortion characteristics of following circuit blocks such as an RF variable-gain amplifier and a mixer, a tunable technique for the LNA is proposed. Then, to improve the sensitivity, spurious signal suppression techniques are also proposed. The single-chip receiver using the proposed techniques is fabricated in 90 nm CMOS technology and total die size is 3.26 mm 3.26 mm. Using the tunable LNA and suppressing undesired spurious signals, the sensitivities of less than -98.6 dBm are achieved for all the channels.

By converting the expression values of each sample into the corresponding rank values, the rank-based approach enables the direct integration of multiple microarray data produced by different laboratories and/or different techniques. In this study, we verify through statistical and experimental methods that informative genes can be extracted from multiple microarray data integrated by the rank-based approach (briefly, integrated rank-based microarray data). First, after showing that a nonparametric technique can be used effectively as a scoring metric for rank-based microarray data, we prove that the scoring results from integrated rank-based microarray data are statistically significant. Next, through experimental comparisons, we show that the informative genes from integrated rank-based microarray data are statistically more significant than those of single-microarray data. In addition, by comparing the lists of informative genes extracted from experimental data, we show that the rank-based data integration method extracts more significant genes than the z-score-based normalization technique or the rank products technique. Public cancer microarray data were used for our experiments and the marker genes list from the CGAP database was used to compare the extracted genes. The GO database and the GSEA method were also used to analyze the functionalities of the extracted genes.

Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.

Duobinary signaling has been introduced into asymmetric multi-chip communications such as DRAM or display interfaces, which allows a controlled amount of ISI to reduce signaling bandwidth by 2/3. A × 2 oversampled equalization has been developed to realize Duobinary signaling. Symbol-rate clock recovery form Duobinary signal has been developed to reduce power consumption for receivers. A Duobinary transmitter test chip was fabricated with 90-nm CMOS process. A 3.5 dB increase in eye height and a 1.5 times increase in eye width was observed.