We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.

Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.

When a cognitive radio system dynamically utilizes a frequency band, channel control information must be communicated over the network in order for the currently available carrier frequencies to be shared. In order to keep efficient spectrum utilization, this control information should also be dynamically transmitted through channels such as cognitive pilot channels based on the channel conditions. If transmitters dynamically select carrier frequencies, receivers must receive the control signal without knowledge of its carrier frequencies. A novel scheme called differential code parallel transmission (DCPT) enables receivers to receive low-rate information without any knowledge of the carrier frequency. The transmitter simultaneously transmits two signals whose carrier frequencies are separated by a predefined value. The absolute values of the carrier frequencies can be varied. When the receiver receives the DCPT signal, it multiplies the signal by a frequency-shifted version of itself; this yields a DC component that represents the data signal, which is then demodulated. However, the multiplication process results in the noise power being squared, necessitating high received signal power. In this paper, to realize a bandpass filter that passes only DCPT signals of unknown frequency and that suppresses noise and interference at other frequencies, a DCPT-adaptive bandpass filter (ABF) that employs an adaptive equalizer is proposed. In the training phase, the received signal is the filter input and the frequency-shifted signal is the training input. Then, the filter is trained to pass the higher-frequency signal of the two DCPT signals. The performance of DCPT-ABF is evaluated through computer simulations. We find that DCPT-ABF operates successfully even under strong interference.

It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as VDD is reduced, a boosted word-voltage scheme is first proposed. Second, Vt variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and Vt variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

In a large queuing system, the effect of the ratio of the filled data on the queue and waiting time from the head of a queue to the service gate are important factors for process efficiency because they are too large to ignore. However, many research works assumed that the factors can be considered to be negligible according to the queuing theory. Thus, the existing queuing models are not applicable to the design of large-scale systems. Such a system could be used as a product classification center for a home delivery service. In this paper, we propose a tree-queue model for large-scale systems that is more adaptive to efficient processes compared to existing models. We analyze and design a mean waiting time equation related to the ratio of the filled data in the queue. Based on simulations, the proposed model demonstrated improvement in process-efficiency, and it is more suitable to realistic system modeling than other compared models for large-scale systems.

We previously proposed a unified wireless system called “Flexible Wireless System”. Comprising of flexible access points and a flexible signal processing unit, it collectively receives a wideband spectrum that includes multiple signals from various wireless systems. In cases of simultaneous multiple signal reception, however, reception performance degrades due to the interference among multiple signals. To address this problem, we propose a new signal separation and reconstruction method for spectrally overlapped signals. The method analyzes spectral information obtained by the short-time Fourier transform to extract amplitude and phase values at each center frequency of overlapped signals at a flexible signal processing unit. Using these values enables signals from received radio wave data to be separated and reconstructed for simultaneous multi-system reception. In this paper, the BER performance of the proposed method is evaluated using computer simulations. Also, the performance of the interference suppression is evaluated by analyzing the probability density distribution of the amplitude of the overlapped interference on a symbol of the received signal. Simulation results confirmed the effectiveness of the proposed method.

We propose a new cognitive radio network architecture using the IP multimedia subsystem (IMS) functionality. We implement the cognitive radio network entities standardized in IEEE 1900.4 on the IMS that exchanges RAN and terminal context information between the networks and the terminals to make optimum and immediate reconfiguration decisions. In our proposed architecture, RAN context information is obtained from cellular networks which are directly connected to the IMS. The presence management functions of the IMS are applied to exchange those information in a “push” manner, which enables immediate notification of changes in wireless environment. We evaluate the performance of the proposed context information exchange method, by comparing with the cases that adequate and immediate RAN context information is not available. The evaluation results show that the proposed framework gives 10–30% superior performance than the conventional cognitive radio networks.

Allowing WLANs to exploit opportunistic spectrum access (OSA) is a promising approach to alleviate spectrum congestion problems in overcrowded unlicensed ISM bands, especially in highly dense WLAN deployments. In this context, novel channel assignment mechanisms jointly considering available channels in both unlicensed ISM and OSA-enabled licensed bands are needed. Unlike classical schemes proposed for legacy WLANs, channel assignment mechanisms for OSA-enabled WLAN should face two distinguishing issues: channel prioritization and spectrum heterogeneity. The first refers to the fact that additional prioritization criteria other than interference conditions should be considered when choosing between ISM or licensed band channels. The second refers to the fact that channel availability might not be the same for all WLAN Access Points because of primary users' activity in the OSA-enabled bands. This paper firstly formulates the channel assignment problem for OSA-enabled WLANs as a Binary Linear Programming (BLP) problem. The resulting BLP problem is optimally solved by means of branch and bound algorithms and used as a benchmark to develop more computationally efficient heuristics. Upon such a basis, a novel channel assignment algorithm based on weighted graph coloring heuristics and able to exploit both channel prioritization and spectrum heterogeneity is proposed. The algorithm is evaluated under different conditions of AP density and primary band availability.

An important and widely considered signal identification technique for cognitive radios is cyclostationarity-based feature detection because this method does not require time and frequency synchronization and prior information except for information concerning cyclic autocorrelation features of target signals. This paper presents the development and experimental evaluation of cyclostationarity-based signal identification equipment. A spatial channel emulator is used in conjunction with the equipment that provides an environment to evaluate realistic spectrum sharing scenarios. The results reveal the effectiveness of the cyclostationarity-based signal identification methodology in realistic spectrum sharing scenarios, especially in terms of the capability to identify weak signals.

This letter proposes an algorithm of determining the BER-minimized block delay for detection and the associated precoder design once the channel state information and limited transmission power are given. Simulation cases demonstrate the adjusting capability of the proposed algorithm for achieving best BER performance of the joint linear transceiver design.

To realize economical optical burst signal receivers for the Optical Network Unit (ONU) of the Ethernet Optical Switched Access Network (E-OSAN), we previously implemented optical burst receivers with AC-coupling and DC-coupling using off-the-shelf components, and showed that the former offers better performance. This paper proposes a new optical burst signal receiver that uses the transfer function, Gn(s) = 1-Hn(s), where Hn(s) denotes a Bessel filter transfer function of order n. We also present a method for designing the proposed receiver and clarify that it has better performance than the conventional AC-coupling one. We then present an LCR circuit synthesis of Gn(s), which is necessary to actually implement a burst receiver based on the proposal.

Let G be a connected graph in which we designate a vertex or a block (a biconnected component) as the center of G. For each cut-vertex v, let Gv be the connected subgraph induced from G by v and the vertices that will be separated from the center by removal of v, where v is designated as the root of Gv. We consider the set R of all such rooted subgraphs in G, and assign an integer, called an index, to each of the subgraphs so that two rooted subgraphs in R receive the same indices if and only if they are isomorphic under the constraint that their roots correspond each other. In this paper, assuming a procedure for computing a signature of each graph in a class of biconnected graphs, we present a framework for computing indices to all rooted subgraphs of a graph G with a center which is composed of biconnected components from . With this framework, we can find indices to all rooted subgraphs of a outerplanar graph with a center in linear time and space.

Recently, the GMPLS controlled WSON has emerged as a promising optical transport network. In order to guarantee the optical signal transmission feature without deformation, the optoelectronic 3R regenerators still need to be sparsely placed in the network, termed as translucent networks. The growing size and complexity of the translucent network requires a transition of control plane to move from the traditional centralized model to a fully distributed architecture in the future. However, centrally designed routing, wavelength assignment, and 3R regenerator allocation approaches become unfeasible under the distributed paradigm due to the outdated and inconsistent network state information. A common solution is to accelerate the update frequency of network state, but the fundamental problem remains that the inaccurate state information is still inevitable. Furthermore, it adds a significant increase to the control traffic volume which adversely degrades the performance and scalability of the network control system. In order to mitigate the impact of having inaccurate state information on network performance in the distributed systems, a novel RWA approach is proposed in this paper, termed as routing and distributed wavelength assignment with top ranked probing wavelength set computation. In our proposal, the wavelength assignment is performed by signalling process with a set of carefully preselected probing wavelengths. This set is dynamically computed based on the resource utilization each time the network state is refreshed. The PCE module is adopted in WSON control plane to be responsible for the computation of RWA and 3R allocation. The performance of the proposed approach is studied by extensive simulations. The experiment results reveal that by employing the proposed scheme, without loss on the blocking performance the inaccuracy of the wavelength availability information can be well tolerated, and the set-up delay in lightpath provisioning can be kept at a low level.

An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

A new near-field source localization algorithm based on a uniform linear array was proposed. The proposed algorithm estimates each parameter separately but does not need pairing parameters. It can be divided into two important steps. The first step is bearing-related electric angle estimation based on the ESPRIT algorithm by constructing a special cumulant matrix. The second step is the other electric angle estimation based on the 1-D MUSIC spectrum. It offers much lower computational complexity than the traditional near-field 2-D MUSIC algorithm and has better performance than the high-order ESPRIT algorithm. Simulation results demonstrate that the performance of the proposed algorithm is close to the Cramer-Rao Bound (CRB).

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.

Conventional algorithms for the joint estimation of carrier frequency offset (CFO) and I/Q imbalance no longer work when the I/Q imbalance depends on the frequency. In order to correct the imbalance across many frequencies, the compensator needed is a filter as opposed to a simple gain and phase compensator. Although, algorithms for estimating the optimal coefficients of this filter exist, their complexity is too high for hardware implementation. In this paper we present a new low complexity algorithm for joint estimation of CFO and frequency dependent I/Q imbalance. For the first part, we derive the estimation scheme using the linear least squares algorithm and examine its floating point performance compared to conventional algorithms. We show that the proposed algorithm can completely eliminate BER floor caused by CFO and I/Q imbalance at a lesser complexity compared to conventional algorithms. For the second part, we examine the hardware complexity in fixed point hardware and latency of the proposed algorithm. Based on BER performance, the circuit needs a wordlength of at least 16 bits in order to properly estimate CFO and I/Q imbalance. In this configuration, the circuit is able to achieve a maximum speed of 115.9 MHz in a Virtex 5 FPGA.

This paper proposes a diversity scheme for Multi-Input Multi-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) based on Radio Frequency (RF) signal processing. Although a 22 MIMO-OFDM system can double the capacity without expanding the occupied frequency bandwidth, we cannot get additional diversity gain using the linear MIMO decomposition method. The proposed method improves the bit error rate (BER) performance by making efficient use of RF signal processing. Computer simulation results show that the proposed scheme gives additional diversity gain.

Federated identity and access management (FIAM) systems enable a user to access services provided by various organizations seamlessly. In FIAM systems, service providers normally stipulate that their users show assertions issued by allied parties to use their services as well as determine user privileges based on attributes in the assertions. However, the integrity of the attributes is important under certain circumstances. In such a circumstance, all released assertions should reflect modifications made to user attributes. Despite the ability to adopt conventional certification revocation technologies, including CRL or OCSP, to revoke an assertion and request the corresponding user to obtain a new assertion, re-issuing an entirely new assertion if only one attribute, such as user location or other environmental information, is changed would be inefficient. Therefore, this work presents a self-adaptive framework to achieve consistency in federated identity and access management systems (SAFIAM). In SAFIAM, an identity provider (IdP), which authenticates users and provides user attributes, should monitor access probabilities according to user attributes. The IdP can then adopt the most efficient means of ensuring data integrity of attributes based on related access probabilities. While Internet-based services emerge daily that have various access probabilities with respect to their user attributes, the proposed self-adaptive framework significantly contributes to efforts to streamline the use of FIAM systems.