In this paper, we introduce generalized feed-forward shift registers (GF2SR) to apply them to secure and testable scan design. Previously, we introduced SR-equivalents and SR-quasi-equivalents which can be used in secure and testable scan design, and showed that inversion-inserted linear feed-forward shift registers (I2LF2SR) are useful circuits for the secure and testable scan design. GF2SR is an extension of I2LF2SR and the class is much wider than that of I2LF2SR. Since the cardinality of the class of GF2SR is much larger than that of I2LF2SR, the security level of scan design with GF2SR is much higher than that of I2LF2SR. We consider how to control/observe GF2SR to guarantee easy scan-in/out operations, i.e., state-justification and state-identification problems are considered. Both scan-in and scan-out operations can be overlapped in the same way as the conventional scan testing, and hence the test sequence for the proposed scan design is of the same length as the conventional scan design. A program called WAGSR (Web Application for Generalized feed-forward Shift Registers) is presented to solve those problems.

Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits.

High-resolution time of arrival (TOA) estimation techniques have great promise for the high range resolution required in recently developed radar systems. A widely known super-resolution TOA estimation algorithm for such applications, the multiple-signal classification (MUSIC) in the frequency domain, has been proposed, which exploits an orthogonal relationship between signal and noise eigenvectors obtained by the correlation matrix of the observed transfer function. However, this method suffers severely from a degraded resolution when a number of highly correlated interference signals are mixed in the same range gate. As a solution for this problem, this paper proposes a novel TOA estimation algorithm by introducing a maximum likelihood independent component analysis (MLICA) approach, in which multiple complex sinusoidal signals are efficiently separated by the likelihood criteria determined by the probability density function (PDF) of a complex sinusoid. This MLICA schemes can decompose highly correlated interference signals, and the proposed method then incorporates the MLICA into the MUSIC method, to enhance the range resolution in richly interfered situations. The results from numerical simulations and experimental investigation demonstrate that our proposed pre-processing method can enhance TOA estimation resolution compared with that obtained by the original MUSIC, particularly for lower signal-to-noise ratios.

The noise in digital images acquired by image sensors has complex characteristics due to the variety of noise sources. However, most noise reduction methods assume that an image has additive white Gaussian noise (AWGN) with a constant standard deviation, and thus such methods are not effective for use with image signal processors (ISPs). To efficiently reduce the noise in an ISP, we estimate a unified noise model for an image sensor that can handle shot noise, dark-current noise, and fixed-pattern noise (FPN) together, and then we adaptively reduce the image noise using an adaptive Smallest Univalue Segment Assimilating Nucleus ( SUSAN ) filter based on the unified noise model. Since our noise model is affected only by image sensor gain, the parameters for our noise model do not need to be re-configured depending on the contents of image. Therefore, the proposed noise model is suitable for use in an ISP. Our experimental results indicate that the proposed method reduces image sensor noise efficiently.

With the rapid expansion of vector data model application to digital content such as drawings and digital maps, the security and retrieval for vector data models have become an issue. In this paper, we present a vector data-hashing algorithm for the authentication, copy protection, and indexing of vector data models that are composed of a number of layers in CAD family formats. The proposed hashing algorithm groups polylines in a vector data model and generates group coefficients by the curvatures of the first and second type of polylines. Subsequently, we calculate the feature coefficients by projecting the group coefficients onto a random pattern, and finally generate the binary hash from binarization of the feature coefficients. Based on experimental results using a number of drawings and digital maps, we verified the robustness of the proposed hashing algorithm against various attacks and the uniqueness and security of the random key.

This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.

Detailed tracking is required for many vision applications. A visual feature-based constraint underlies most conventional motion estimation methods. For example, optical flow methods assume that the brightness of each pixel is constant in two consecutive frames. However, it is difficult to realize accurate extraction and tracking using only visual feature information, because viewpoint changes and inconsistent illumination cause the visual features of some regions of objects to appear different in consecutive frames. A structure-based constraint of objects is also necessary for tracking. In the proposed method, both visual feature matching and structure matching are formulated as a linear assignment problem and then integrated.

In this paper, we present the validity and potential capacity of a modeling and simulation environment for the nonresonant plasmonic terahertz (THz) detector based on the silicon (Si) field-effect transistor (FET) with a technology computer-aided design (TCAD) platform. The nonresonant and “overdamped” plasma-wave behaviors have been modeled by introducing a quasi-plasma electron charge box as a two-dimensional electron gas (2DEG) in the channel region only around the source side of Si FETs. Based on the coupled nonresonant plasma-wave physics and continuity equation on the TCAD platform, the alternate-current (AC) signal as an incoming THz wave radiation successfully induced a direct-current (DC) drain-to-source output voltage as a detection signal in a sub-THz frequency regime under the asymmetric boundary conditions with a external capacitance between the gate and drain. The average propagation length and density of a quasi-plasma have been confirmed as around 100 nm and 11019/cm3, respectively, through the transient simulation of Si FETs with the modulated 2DEG at 0.7 THz. We investigated the incoming radiation frequency dependencies on the characteristics of the plasmonic THz detector operating in sub-THz nonresonant regime by using the quasi-plasma modeling on TCAD platform. The simulated dependences of the photoresponse with quasi-plasma 2DEG modeling on the structural parameters such as gate length and dielectric thickness confirmed the operation principle of the nonresonant plasmonic THz detector in the Si FET structure. The proposed methodologies provide the physical design platform for developing novel plasmonic THz detectors operating in the nonresonant detection mode.

This paper presents a novel color descriptor based on the proposed Color Barycenter Hexagon (CBH) model for automatic Road-Sign (RS) detection. In the visual Driver Assistance System (DAS), RS detection is one of the most important factors. The system provides drivers with important information on driving safety. Different color combinations of RS indicate different functionalities; hence a robust color detector should be designed to address color changes in natural surroundings. The CBH model is constructed with barycenter distribution in the created color triangle, which represents RS colors in a more compact way. For detecting RS, the CBH model is used to segment color information at the initial step. Furthermore, a judgment process is applied to verify each RS candidate through the size, aspect ratio, and color ratio. Experimental results show that the proposed method is able to detect RS with robust, accurate performance and is invariant to light and scale in more complex surroundings.

In this paper we establish a secure communication model where eavesdropper and intended receiver have multiple antennas. We use cooperation and jamming to achieve physical layer security. First, we study how to allocate power between the information bearing signal and the jamming signal. Second, based on this model, we also jointly optimize both the information bearing signal weights and the jamming signal weights to improve physical layer security. The optimal power allocation and the weights are obtained via an iteration algorithm to maximize the secrecy rate. Comparing with equal power allocation and some other different methods, it shows that using cooperative relaying and jamming can significantly improve the physical layer security from the simulation results.

We propose an efficient network design algorithm that realizes shared protection. The algorithm iteratively improves the degree of wavelength resource usage and fiber utilization. To achieve this, we newly define two metrics to evaluate the degree of wavelength resource usage of a pair of working/backup paths and the fiber utilization efficiency. The proposed method iteratively redesigns groups of paths that are selected in the order determined by the metrics. A numerical analysis verifies that the proposed algorithm can substantially reduce the required wavelength resources and hence fiber cost. It is also verified that the computational complexity of the proposed algorithm is small enough to terminate within practicable time.

This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations. The proposed associativity-reconfigurable cache consists of pairs of cache ways so that it can exploit the recovery feature of the novel 7T/14T SRAM cell. Each pair has two operating modes that can be selected based upon the required voltage level of current operating conditions: normal mode for high performance and dependable mode for reliable low-voltage operations. We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages. Meanwhile leaving stronger pairs in the normal mode, we can minimize performance losses. Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage. Moreover, it can decrease the minimum operating voltage by 140 mV achieving 67.48% and 26.70% reduction of the power dissipation and energy per instruction. Processor simulation results show that designing the on-chip caches using the proposed scheme results in 2.95% maximum IPC losses, but it can be chosen various performance levels. Area estimation results show that the proposed cache adds area overhead of 1.61% and 5.49% in 32-KB and 256-KB caches, respectively.

This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

This paper proposes an ASIC design support tool set for non-pipelined asynchronous circuits with bundled-data implementation. This tool set consists of seven tools to automate design processes of bundled-data implementation such as the generation of design constraints, timing verification, and delay adjustment considering a given latency constraint. With the proposed design flow which combines the proposed tool set and commercial CAD tools, most of design processes from an RTL model is fully automated. In the experiments, to show the effectiveness of energy consumption in bundled-data implementation compared to synchronous counterpart, this paper synthesizes several circuits with a latency constraint which is generated from the synchronous counterpart with the minimum clock cycle time.

This paper presents a novel decision feedback equalizer (DFE) with block delay detection for the joint transceiver design that uses channel state information (CSI). The block delay detection in the proposed DFE offers a degree of freedom for optimizing the precoder of the transmitter, provided the transmission power is constrained. In the proposed DFE, the feedforward matrix is devised to enable a block-based equalizer that can be cooperated with an intrablock decision feedback equalizer for suppressing the intersymbol interference (ISI) for the transmitted block with a certain block delay. In this design, the interblock interference (IBI) for the delay block is eliminated in advance by applying the recently developed oblique projection framework to the implementation of the feedforward matrix. With knowledge of full CSI, the block delay and the associated block-based precoder are jointly designed such that the average bit-error-rate (BER) is minimized, subject to the transmission power constraint. Separate algorithms are derived for directly determining the BER-minimized block delays for intrablock minimum mean-squared error (MMSE) and zero-forcing (ZF) equalization criteria. Theoretical derivations indicate that the proposed MMSE design simultaneously maximize the Gaussian mutual information of a transceiver, even under the cases of existing IBI. Simulation results validate the proposed DFE for devising an optimum transceiver with CSI, and show the superior BER performance of the optimized transceiver using proposed DFE. Relying on analytic results and simulation cases also builds a sub-optimum MMSE design of the proposed DFE using the BER-minimized block delay for ZF criterion, which exhibits almost identical BER performance as the proposed MMSE design in most of the signal-to-noise ratio (SNR) range.

This survey provides a brief introduction to compressed sensing as well as several major algorithms to solve it and its various applications to communications systems. We firstly review linear simultaneous equations as ill-posed inverse problems, since the idea of compressed sensing could be best understood in the context of the linear equations. Then, we consider the problem of compressed sensing as an underdetermined linear system with a prior information that the true solution is sparse, and explain the sparse signal recovery based on 1 optimization, which plays the central role in compressed sensing, with some intuitive explanations on the optimization problem. Moreover, we introduce some important properties of the sensing matrix in order to establish the guarantee of the exact recovery of sparse signals from the underdetermined system. After summarizing several major algorithms to obtain a sparse solution focusing on the 1 optimization and the greedy approaches, we introduce applications of compressed sensing to communications systems, such as wireless channel estimation, wireless sensor network, network tomography, cognitive radio, array signal processing, multiple access scheme, and networked control.

Let Gs=(Vs, Es) be a simple connected graph. A vertex v ∈ Vs is an articulation vertex if deletion of v and its incident edges from Gs disconnects the graph into at least two connected components. Finding all articulation vertices of a given graph is called the articulation vertex problem. A vertex u ∈ Vs is called a hinge vertex if there exist any two vertices x and y in Gs whose distance increase when u is removed. Finding all hinge vertices of a given graph is called the hinge vertex problem. These problems can be applied to improve the stability and robustness of communication network systems. In this paper, we propose linear time algorithms for the articulation vertex problem and the hinge vertex problem of circular permutation graphs.

Observing the security of existing identity-based proxy signature schemes was proven in the random oracle model, Cao et al. proposed the first direct construction of identity-based proxy signature secure in the standard model by making use of the identity-based signature due to Paterson and Schuldt. They also provided a security proof to show their construction is secure against forgery attacks without resorting to the random oracles. Unfortunately, in this letter, we demonstrate that their scheme is vulnerable to insider attacks. Specifically, after a private-key extraction query, an adversary, behaving as a malicious original signer or a malicious proxy signer, is able to violate the unforgeability of the scheme.

This paper presents an architecture of signal-dependent analog-to-digital converter (ADC) based on MINIMAX sampling scheme that allows achieving high data compression rate and power reduction. The proposed architecture consists of a conventional synchronous ADC, a timer and a peak detector. AD conversion is carried out only when input signal peaks are detected. To improve the accuracy of signal reconstruction, MINIMAX sampling is improved so that multiple points are captured for each peak, and its effectiveness is experimentally confirmed. In addition, power reduction, which is the primary advantage of the proposed signal-dependent ADC, is analytically discussed and then validated with circuit simulations.

We report a 40-Gb/s and highly accurate intensity limiter with a single Erbium-Doped Fiber Amplifier (EDFA) for low-power-consumption driving intensity limiting. The intensity limiter based on self-phase modulation with an appropriate pre-chirping procedure makes it possible, which provides a highly accurate limiting of less than 0.01 dB. We fed 40-Gb/s signals with 2.69 dB intensity fluctuation and 4.7 dB improvement on the receiver sensitivity was obtained for a bit error rate of 10-9 by using a numerical simulation.