This paper presents an implementation of a digital chaotic signal generator based on compound one-dimensional sinusoidal maps. The proposed chaotic map not only offers high chaoticity measured from a positive lyapunov exponent but also provides diverse bifurcation structures with robust chaos over most regions of parameter spaces. Implementation on FPGA realizes small number of components and offers a highly random chaotic sequence with no autocorrelation. The proposed chaotic signal generator offers a potential alternative in random test pattern generation or in secured data communication applications.

A fast and accurate architecture exploration for high performance and low energy VLIW data-path is proposed. The main contribution is a method to find Pareto optimal FU structures, i.e., the optimal number of FUs and the best instruction assignment for each FU. The proposed architecture exploration method is based on GA and enables the effective exploration of vast solution space. Experimental results showed that proposed method was able to achieve fast and accurate architecture exploration. For most cases, the estimation error was less than 1%.

Spectrum sensing is one of the methods to identify available white spaces for secondary usage which was specified by the regulators. However, signal quality to be sensed can plunge to a very low signal-to-noise-ratio due to signal propagation and hence readings from individual sensors will be unreliable. Distributed sensing by the cooperation of multiple sensors is one way to cope with this problem because the diversity gain due to the combining effect of data captured at different position will assist in detecting signals that might otherwise not be detected by a single sensor. In effect, the probability of detection can be improved. We have implemented a distributed sensing system to evaluate the performance of different cooperative sensing algorithms. In this paper we describe our implementation and measurement experience which include the system design, specification of the system, measurement method, the issues and solutions. This paper also confirms the performance enhancement offered by distributed sensing algorithms, and describes several ideas for further enhancement of the sensing quality.

This paper describes an analytical study of performance of a proposed signal detection scheme that will allow coexistence of an additional radio communication system (generally, secondary system) in the service area where the existing communication system (primary system) is operated. Its performance characteristics are derived by an analytical method based on stochastic theory, which is subsequently validated by software simulation. The main purpose of the detection scheme is to protect the primary system from the secondary system. In such a situation, the signals of the primary system and secondary system may be simultaneously received in the signal detector. One application of such a scheme is D-to-D (Device-to-Device) communication, whose system concept including the detection scheme is briefly introduced. For improved secondary signal detection, we propose the signal cancellation method of the primary system and the feature detection method of the secondary system signal. We evaluate the performance characteristics of the detection scheme in terms of “probability of correct detection”. We reveal that an undesired random component is produced in the feature detection procedure when two different signals are simultaneously received, which degrades the detection performance. Such undesired component is included in the analytical equations. We also clarify that the cancellation scheme improves the performance, when the power ratio of the primary signal to secondary signal is higher than 20-22dB.

Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, in conventional methods, manual- and visual-based checks are required to locate pins and tune the geometries of layouts. These tasks can be very time consuming and unreliable. In this work, an O(Nlog N) redundant via-aware standard cell optimization scheme is developed. The proposed method is an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design time for standard cells. The optimized SCs effectively increase the redundant via insertion rate, and in particular the insertion rate of via1 for both concurrent routing and post-layout optimization. Furthermore, an automatic layout checker and optimizer are more efficient in identifying expandable metal 1 pins in libraries that contain numerous cells than are conventional visual check and manual optimization. Therefore, the proposed scheme not only solves the problem of a low via1 insertion rate in nanometer regimes, but also provides an efficient layout optimizer for designing standard cells. Experimental results indicate that the optimized standard cells increase the double-via1 insertion rates by 21.9%.

This paper presents an experimental evaluation of an ocean wave remote sensing system that uses bistatic GPS signal reflection to estimate wave characteristics. In our previous paper, a bistatic ocean wave remote sensing system by GPS was proposed to estimate the characteristics of sea swell near a harbor, and was also evaluated by numerical simulations. In the next phase, a prototype system has been developed and some basic experiments have been carried out in a coastal area in order to evaluate the system experimentally. In this paper, we will outline the prototype system. The system mainly consists of an array antenna, a front-end, and an estimator for ocean wave characteristics. Next, we explain that the estimator for ocean wave characteristics can identify each signal reflected from the ocean waves. Finally, the experiments show that the prototype system can receive the reflected signals from the sea-surface near the coast, and estimate the wave period and wavelength in the direction of the array antenna.

Conventional adaptive notch filter based on an infinite impulse response (IIR) filter is well known. However, this kind of adaptive notch filter has a problem of stability due to its adaptive IIR filter. In addition, tap coefficients of this notch filter converge to solutions with bias error. In order to solve these problems, an adaptive notch filter using Fourier sine series (ANFF) is proposed. The ANFF is stable because an adaptive IIR filter is not used as an all-pass filter. Further, the proposed adaptive notch filter is robust enough to overcome effects of a disturbance signal, due to a structure of the notch filter based on an exponential filter and line symmetry of auto correlation.

This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on double-gate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.

Multiple access (MA) technology is of most importance for beyond long term evolution (LTE) system. Non-orthogonal multiple access (NOMA) utilizing power domain and advanced receiver has been considered as a candidate MA technology recently. In this paper, power assignment method, which plays a key role in performance of NOMA, is investigated. The power assignment on the basis of maximizing geometric mean user throughput requires exhaustive search and thus has an unacceptable computational complexity for practical systems. To solve this problem, a novel power assignment method is proposed by exploiting tree search and characteristic of serial interference cancellation (SIC) receiver. The proposed method achieves the same performance as the exhaustive search while greatly reduces the computational complexity. On the basis of the proposed power assignment method, the performance of NOMA is investigated by link-level and system-level simulations in order to provide insight into suitability of using NOMA for future MA. Simulation results verify effectiveness of the proposed power assignment method and show NOMA is a very promising MA technology for beyond LTE system.

Multivariate Public Key Cryptosystems (MPKC) are candidates for post-quantum cryptography. Rainbow is a digital signature scheme in MPKC, whose signature generation and verification are relatively efficient. However, the security of MPKC depends on the difficulty in solving a system of multivariate polynomials, and the key length of MPKC becomes substantially large compared with that of RSA cryptosystems for the same level of security. The size of the secret and public keys in MPKC has been reduced in previous research. The NC-Rainbow is a signature scheme in MPKC, which was proposed in order to reduce the size of secret key of Rainbow. So far, several attacks against NC-Rainbow have been proposed. In this paper, we summarize attacks against NC-Rainbow, containing attacks against the original Rainbow, and analyze the total security of NC-Rainbow. Based on the cryptanalysis, we estimate the security parameter of NC-Rainbow at the several security level.

An effective interlaced-to-progressive scanning format conversion method is presented for the interpolation of interlaced images. On the basis of the weight assignment algorithm, the proposed method is composed of three stages: (1) straightforward interpolation with pre-determined six-tap filter, (2) fuzzy metric-based weight assignment, (3) updating the interpolation results. We first deinterlace the missing line with six-tap filter in the working window. Then we compute the local weight among the adjacent pixels with a fuzzy metric. Finally we deinterlace the missing pixels using the proposed interpolator. Comprehensive simulations conducted on different images and video sequences have proved the effectiveness of the proposed method, with significant improvement over conventional methods.

Verifiable random functions (VRF), proposed in 1999, and selectively convertible undeniable signature (SCUS) schemes, proposed in 1990, are apparently thought as independent primitives in the literature. In this paper, we show that they are tightly related in the following sense: VRF is exactly SCUS; and the reverse also holds true under a condition. This directly yields several deterministic SCUS schemes based on existing VRF constructions. In addition, we create a new probabilistic SCUS scheme, which is very compact. We build efficient confirmation and disavowal protocols for the proposed SCUS schemes, based on what we call zero-knowledge protocols for generalized DDH and non-DDH. These zero-knowledge protocols are built either sequential, concurrent, or universally composable.

A recursive construction of (k+1)-ary error-correcting signature code is proposed to identify users for MAAC, even in the presence of channel noise. The recursion is originally from a trivial signature code. In the (j-1)-th recursion, from a signature code with minimum distance of 2j-2, a longer and larger signature code with minimum distance of 2j-1 is obtained. The decoding procedure of signature code is given, which consists of error correction and user identification.

TSV-interconnected 3D chips face problems such as high cost, low yield and large power dissipation. We propose a wireless 3D on-chip-network architecture for application-specific SoC design, using inductive-coupling interconnect instead of TSV for inter-layer communication. Primary design challenge of inductive-coupling 3D SoC is allocating wireless links in the 3D on-chip network effectively. We develop a design flow fully exploiting the design space brought by wireless links while providing flexible tradeoff for user's choice. Experimental results show that our design brings great improvement over uniform design and Sunfloor algorithm on latency (5% to 20%) and power consumption (10% to 45%).

Scheduling plays a key role in MapReduce systems. In this paper, we explore the efficiency of an MapReduce cluster running lots of independent and continuously arriving MapReduce jobs. Data locality and load balancing are two important factors to improve computation efficiency in MapReduce systems for data-intensive computations. Traditional cluster scheduling technologies are not well suitable for MapReduce environment, there are some in-used schedulers for the popular open-source Hadoop MapReduce implementation, however, they can not well optimize both factors. Our main objective is to minimize total flowtime of all jobs, given it's a strong NP-hard problem, we adopt some effective heuristics to seek satisfied solution. In this paper, we formalize the scheduling problem as job selection problem, a load balance aware job selection algorithm is proposed, in task level we design a strict data locality tasks scheduling algorithm for map tasks on map machines and a load balance aware scheduling algorithm for reduce tasks on reduce machines. Comprehensive experiments have been conducted to compare our scheduling strategy with well-known Hadoop scheduling strategies. The experimental results validate the efficiency of our proposed scheduling strategy.

This paper propose a structure of standard cells where the P/N boundary ratio of each cell can be independently customized for near-threshold operation. Lowering the supply voltage is one of the most promising approaches for reducing the power consumption of VLSI circuit, however, this causes an increase of imbalance between rise and fall delays for cells having transistor stacks. Conventional cell library with fixed P/N boundary is not efficient to compensate this delay imbalance. Proposed structure achieves individual P/N boundary ratio optimization for each standard cell, therefore it cancels the imbalance between rise and fall delays at the expense of cell area. Proposed structure is verified using measured result of Ring Oscillator circuits and simulation result of benchmark circuits in 65nm CMOS. The experiments with ISCAS'85 benchmark circuits demonstrate that the standard cell library consisting of the proposed cells reduces the power consumption of the benchmark circuits by 16% on average without increasing the circuit area, compared to that of the same circuit synthesized with a library which is not optimized for the near-threshold operation.

This paper proposes an improved color barycenter model (CBM) and its separation for automatic road sign (RS) detection. The previous version of CBM can find out the colors of RS, but the accuracy is not high enough for separating the magenta and blue regions and the influence of number with the same color are not considered. In this paper, the improved CBM expands the barycenter distribution to cylindrical coordinate system (CCS) and takes the number of colors at each position into account for clustering. Under this distribution, the color information can be represented more clearly for analyzing. Then aim to the characteristic of barycenter distribution in CBM (CBM-BD), a constrained clustering method is presented to cluster the CBM-BD in CCS. Although the proposed clustering method looks like conventional K-means in some part, it can solve some limitations of K-means in our research. The experimental results show that the proposed method is able to detect RS with high robustness.

This paper proposes a novel design method involving the stages from analog circuit design to layout synthesis in hope of suppressing the process-induced variations with a design style called transistor array. We manage to decompose the transistors into unified sub-transistors, and arrange the sub-transistors on a uniform placement grid so that a better post-CMP profile is expected to be achieved, and that the STI-stress is evened up to alleviate the process variations. However, since lack of direct theoretical support to the transistor decomposition, we analyze and evaluate the errors arising from the decomposition in both large and small signal analysis. A test chip with decomposed transistors on it confirmed our analysis and suggested that the errors are negligibly small and the design with transistor array is applicable. Based on this conclusion, a design flow with transistor array covering from circuit design to layout synthesis is proposed, and several design cases, including three common-source amplifiers, three two-stage OPAMPS and a nano-watt current reference, are implemented on a test chip with the proposed method, to demonstrate the feasibility of our idea. The measurement results from the chip confirmed that the designs with transistor array are successful, and the proposed method is applicable.

The optimum generalized partial response (GPR) target for barium ferrite (BaFe) tape systems was studied. The shift in perpendicular magnetic recording technology in HDDs to systems employing single-pole-type (SPT) recording heads and media with a soft under layer (SUL) has been accompanied by a change in the read channel design, whereas current magnetic tape recording systems utilize a combination of a ring-type recording head with a single magnetic layer structured medium. Therefore, the read channel performance of current oriented BaFe particulate tape systems needs to be studied to best exploit the potential of this medium. Toward this end, DC-free, DC-full, and DC-suppressed targets were compared. The results show that assuming a GPRML detector with 16 or more states, a traditional DC-free target exhibits the best bit error rate performance for both longitudinally and perpendicularly oriented BaFe media, suggesting that the current read channel designed for longitudinally oriented media can also be utilized for BaFe particulate tape systems.

The main target of compressed sensing is recovery of one-dimensional signals, because signals more than two-dimension can also be treated as one-dimensional ones by raster scan, which makes the sensing matrix huge. This is unavoidable for general sensing processes. In separable cases like discrete Fourier transform (DFT) or standard wavelet transforms, however, the corresponding sensing process can be formulated using two matrices which are multiplied from both sides of the target two-dimensional signals. We propose an approximate message passing (AMP) algorithm for the separable sensing process. Typically, we suppose DFT for the sensing process, in which the measurements are complex numbers. Therefore, the formulation includes cases in which both target signal and measurements are complex. We show the effectiveness of the proposed algorithm by computer simulations.