A self-calibrating per-pin phase adjuster, which does not require any feedback from the slave chip and a multi-phase clock in the master and slave chips, is proposed for a high speed parallel chip-to-chip interface with a source synchronous double data rate (DDR) signaling. It achieves not only per-pin phase adjustment but also 90° phase shift of a strobe signal for a source synchronous DDR signaling. For this self-calibration, the phase adjuster measures and compensates the only relative mismatched delay among channels by utilizing on-chip time-domain reflectometry (TDR). Thus, variable delay lines, finite state machines, and a test signal generator are additionally required for the proposed phase adjuster. In addition, the power-gating receiver is used to reduce the discontinuity effect of the channel including parasitic components of chip package. To verify the proposed self-calibrating per-pin phase adjuster, the transceivers with 16 data, strobe, and clock signals for the interface with a source synchronous DDR signaling were implemented by using a 60 nm 1-poly 3-metal CMOS DRAM process with a 1.5 V supply. Each phase skew between Strobe and 16 Data was corrected within 0.028UI at 1.6-Gb/s data rate in a point-to-point channel.

Background subtraction is widely used in detecting moving objects; however, changing illumination conditions, color similarity, and real-time performance remain important problems. In this paper, we introduce a sequential method for adaptively estimating background components using Kalman filters, and a novel method for detecting objects using margined sign correlation (MSC). By applying MSC to our adaptive background model, the proposed system can perform object detection robustly and accurately. The proposed method is suitable for implementation on a graphics processing unit (GPU) and as such, the system realizes real-time performance efficiently. Experimental results demonstrate the performance of the proposed system.

Iris recognition is an important biometric method for personal identification. The accuracy of an iris recognition system highly depends on the success of an iris segmentation step. In this paper, a robust and accurate iris segmentation algorithm for closed-up NIR eye images is developed. The proposed method addressed problems of different characteristics of iris databases using local image properties. A precise pupil boundary is located with an adaptive thresholding combined with a gradient-based refinement approach. A new criteria, called a local signal-to-noise ratio (LSNR) of an edge map of an eye image is proposed for localization of the iris's outer boundary. The boundary is modeled with a weighted circular integral of LSNR optimization technique. The proposed method is experimented with multiple iris databases. The obtained results demonstrated that the proposed iris segmentation method is robust and desirable. The proposed method accurately segments iris region, excluding eyelids, eyelashes and light reflections against multiple iris databases without parameter tunings. The proposed iris segmentation method reduced false negative rate of the iris recognition system by half, compared to results obtained using Masek's method.

A 2 GHz gain equalizer for analog signal transmission using a novel gain compensation method is described in this paper. This method is based on feedforward compensation by a low-pass filter, which improves the gain-equalizing performance by subtracting low-pass filtered signals from the directly passed signal at the end of a transmission line. The advantage of the proposed method over the conventional one is that the gain is equalized with a smaller THD at higher frequencies by using a low-pass instead of a high-pass filter. In this circuit, the peak gain is adjustable from 0 to 2.4 dB and the frequency of the peak gain can be controlled up to 2 GHz by varying the value of an external capacitor. Also this circuit achieves THD with 5 dB better than the conventional circuits.

In this paper, we analyze the impact of channel estimation errors for both decode-and-forward (DF) and amplify-and-forward (AF) cooperative communication systems over Nakagami-m fading channels. Firstly, we derive the exact one-integral and the approximate expressions of the symbol error rate (SER) for DF and AF relay systems with different modulations. We also present expressions showing the limitations of SER under channel estimation errors. Secondly, in order to quantify the impact of channel estimation errors, the average signal-to-noise-ratio (SNR) gap ratio is investigated for the two types of cooperative communication systems. Numerical results confirm that our theoretical analysis for SER is very efficient and accurate. Comparison of the average SNR gap ratio shows that DF model is less susceptible to channel estimation errors than AF model.

A neuro fuzzy method to design analog circuits is explained, where the universe of discourse of the fuzzy system is adjusted by means of a self-organized artificial neural network. As an example of this approach, an op-amp is optimized in order to hold a predetermined aim; where the unity gain bandwidth is an objective of design, and the restrictions of open-loop gain and margin phase are treated as objectives too. Firstly, the experience of the behavior of the circuit is obtained, hence an inference system is constructed and a neural network is applied to achieve a faster convergence into a desired solution. This approach is characterized by having a simple implementation, a very natural understanding and a better performance than static methods of fuzzy optimization.

Undeniable signatures, introduced by Chaum and van Antwerpen, require a verifier to interact with the signer to verify a signature, and hence allow the signer to control the verifiability of his signatures. Convertible undeniable signatures, introduced by Boyar, Chaum, Damgård, and Pedersen, furthermore allow the signer to convert signatures to publicly verifiable ones by publicizing a verification token, either for individual signatures or for all signatures universally. In addition, the original definition allows the signer to delegate the ability to prove validity and convert signatures to a semi-trusted third party by providing a verification key. While this functionality is implemented by the early convertible undeniable signature schemes, most recent schemes do not consider this form of delegation despite its practical appeal. In this paper we present an updated definition and security model for schemes allowing delegation, and furthermore highlight a new essential security property, token soundness, which is not formally treated in the previous security models for convertible undeniable signatures. We then propose a new convertible undeniable signature scheme. The scheme allows delegation of verification and is provably secure in the standard model assuming the computational co-Diffie-Hellman problem, a closely related problem, and the decisional linear problem are hard. Furthermore, unlike the recently proposed schemes by Phong et al. and Huang et al., our scheme provably fulfills all security requirements while providing short signatures.

In this letter, we propose a new observer error linearization approach that is called reduced-order dynamic observer error linearization (RDOEL), which is a modified version of dynamic observer error linearization (DOEL). We introduce the concepts and properties of RDOEL, and provide a complete solution to RDOEL with one integrator. Moreover, we show that it is also a complete solution to a simple case of DOEL.

A sanitizable signature scheme is a signature scheme which, after the signer generates a valid signature of a message, allows a specific entity (sanitizer) to modify the message for hiding several parts. Existing sanitizable signature schemes require the message to be divided into pre-defined blocks before signing so that each block can be sanitized independently. However, there are cases where the parts of the message which are needed to be sanitized can not be determined in the time of signing. Thus, it is difficult to decide the partition of the blocks in such cases. Since the length of the signature is usually proportional to the number of blocks, signing every bit independently will make the signature too long. In this paper, we propose a solution by introducing a new concept called sequential bitwise sanitizable signature schemes, where any sequence of bits of the signed document can be made sanitizable without pre-defining them, and without increasing the length of signature. We also show that a one-way permutation suffices to get a secure construction, which is theoretically interesting in its own right, since all the other existing schemes are constructed using stronger assumptions.

Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.

In this paper, the performance of the soft-decision-and-forward (SDF) protocol in the cooperative communication network with one source, one relay, and one destination, where each node has two transmit and receive antennas, is analyzed in terms of the bit error rate (BER) obtained from the pairwise error probability (PEP). Using the moment generating function and Q-function approximation, the PEP of SDF protocol is calculated and we confirm that the SDF with two antennas achieves the full diversity order. For the slow-varying Rayleigh fading channel, the optimal power allocation ratio can be determined so as to minimize the average PEP (or BER). Due to the difficulty of deriving the optimal value analytically, an alternative strategy of maximizing the product signal-to-noise ratio (SNR) of direct and relay links, which we call the suboptimal power allocation, is considered. Through a numerical analysis, we show that the performance gap between the suboptimal and optimal power allocation strategies is negligible in the high SNR region.

Recently, Jin, Wen, and Du proposed an identity-based signcryption scheme in the standard model. In this letter, we show that their scheme does not have the indistinguishability against adaptive chosen ciphertext attacks and existential unforgeability against adaptive chosen messages attacks.

A BICM-ID system with 3-dimensional rotated BPSK constellation and signal space diversity (SSD) is proposed to combat the effect of Rayleigh fading. A new criterion based on mutual information is proposed to find the optimal rotation matrix, and the labeling that fits well with the outer code is presented. Simulation results show that at BER of 10-5 over a Rayleigh fading channel, with the code length of 192,000 bits and the iteration number of 100, the performance of the proposed system is only about 0.8 dB from the Gaussian-input Shannon limit and exceeds the limit constrained by the traditional QPSK input without rotation or SSD, at the spectrum efficiency of 1 bit/s/Hz.

Advanced Evolved Universal Terrestrial Radio Access (Advanced E-UTRA), called LTE-Advanced, has been standardized in the 3rd Generation Partnership Project (3GPP) as a candidate for IMT-Advanced. LTE-Advanced supports spatial orthogonal-resource transmit diversity (SORTD) [1],[2] for ACK/NACK signals and scheduling requests (SRs), which are used to control downlink hybrid automatic repeat requests (HARQs) and manage uplink radio resources based on uplink data traffic, respectively. Both ACK/NACK signals and SRs are carried via a physical uplink control channel (PUCCH) [3], and a common PUCCH format is used for both ACK/NACK signals and SRs. If SORTD is used, the base station assigns mutually orthogonal resources to each antenna included in the user equipment (UE) for ACK/NACK signals and SRs; hence, the number of required resources increases with the number of transmitting antennas in the UE. In this paper, we study the resource reduction method for ACK/NACK signal and SR in case of SORTD using the concept of common resource. In addition, we investigate a phase rotation scheme for common resources to improve the SR detection performance.

ICA (Independent Component Analysis) has a remarkable capability of separating mixtures of stochastic random signals. However, we often face problems of separating mixtures of deterministic signals, especially sinusoidal signals, in some applications such as radar systems and communication systems. One may ask if ICA is effective for deterministic signals. In this paper, we analyze the basic performance of ICA in separating mixtures of complex sinusoidal signals, which utilizes the fourth order cumulant as a criterion of independency of signals. We theoretically show that ICA can separate mixtures of deterministic sinusoidal signals. Then, we conduct computer simulations and radio experiments with a linear array antenna to confirm the theoretical result. We will show that ICA is successful in separating mixtures of sinusoidal signals with frequency difference less than FFT resolution and with DOA (Direction of Arrival) difference less than Rayleigh criterion.

This paper proposes a method to incorporate the concept of time for the inclusion of dynamics of signaling pathway in a Petri net model, i.e., to use timed Petri nets. Incorporation of delay times into a Petri net model makes it possible to conduct quantitative evaluation on a target signaling pathway. However, experimental data describing detailed reactions are not available in most cases. An algorithm given in this paper determines delay times of a timed Petri net only from the structural information of it. The suitability of this algorithm has been confirmed by the results of an application to the IL-1 signaling pathway.

This paper investigates primary signal detection by using a quiet period (QP) in cognitive wireless communications. In particular, we provide an analytical model for studying the impact of QPs on the system performance. Our analysis shows that two successive QPs have a significant impact on system performance. Moreover, the analytical results obtained reveal an optimum period of two successive QPs that maximize system performance.

The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce the redundant via allocation problem for layer partition-based redundant via insertion methods [1] and solve it using the genetic algorithm. At the same time, we use a convex-cost flow model to equilibrate the via density, which is good for the via density rules. The results of layer partition-based model depend on the partition and processing order of metal layers. Furthermore, even we try all of partitions and processing orders, we might miss the optimal solutions. By introducing the redundant via allocation problem on partitioning boundaries, we can avoid the sub-optimality of the original layer-partition based method. The experimental results show that the proposed method got 12 more redundant vias inserted on average and the via density balance can be greatly improved.

This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.

The increase in the time required for data processing, mask drawing, and inspection of photomask, has led to substantial increase in mask manufacturing cost. This has become one of the major challenges in the semiconductor industry. We have developed a data flow process for mask manufacturing in which we refer to design intent information in order to reduce TAT of mask manufacturing processes. We convert design level information "Design Intent (DI)" into priority information of mask manufacturing data known as "Mask Data Rank (MDR)" so that we can identify and sort out the importance of mask patterns from the view point of the design side. As a result, we can reduce mask writing time and mask inspection time. Our objective is to build efficient data flow conversion system from DI to MDR. In this paper we introduce the idea of MDR and the software system that we built for DI extraction. Then we show the experimental results with actual chip data. Lastly we will discuss related issues and their solutions.