The design of the analog part of a mixed analog-digital IC for a commercial wireless burglar alarm system is presented as an example of a very low-power VLSI design for battery-operated systems. The main constraint is battery life, which must be at least five years (with standard camera-battery). An operational amplifier, a power supply monitor and an oscillator are the core of the design. The operational amplifier absorbs 1.5 µA while the entire analog part absorbs 4 µA. Measures on each single part show compliance with specification. Test on working environment show its full functionality. Even though the example is application specific, the design solutions and each single element can also be utilized in many other battery-operated low-frequency devices (e.g. environmental parameter monitoring).

The CDMA/NC-PRMA protocol has been proposed to deal with multimedia traffic flexibly in mobile communications systems. The Load-Balancing (LB) method has been investigated for information slot assignment in CDMA/NC-PRMA systems. However, the LB method may be not effective in multi-cell environments due to inter-cell interference although this method is effective for single cell environments. In this paper, we propose new information slot assignment methods for multi-cell environments; a total reception power based assignment method and a signal to interference ratio (SIR) based assignment method. The former one assigns information slots based on the total reception power from both inside and outside the cell for each slot in the previous frame. The latter one predicts the SIR of receiving packets and assigns information slots to MSs only when predicted SIR exceeds the target SIR. The results of computer simulation show that the proposed schemes have superior transmission performance to the conventional scheme.

A novel optical modulation scheme is proposed for synthesizing a pair of dual-mode optical BPSK signals with an orthogonal phase relationship via a LiNbO3 Mach-Zehnder modulator (MZM) with dual RF signal inputs and a carrier suppression feature, which enables the generation of a crosstalk-free QPSK signal at the photodetection stage. With this method, one can compensate the drawback, that is bandwidth broadening, in our previously proposed method where a dual-mode optical QPSK signal is generated on the basis of narrow-angle modulated QPSK signal injection into a double-sideband suppressed carrier MZM device. We have carried out experiments for 60 GHz performance demonstration of this QPSK signal generation mechanism, and the results indicate the effectiveness of the present scheme.

In our previous research, we proposed a nonlinear digital filter to Estimate the Smoothed and Differential values of the sensor inputs by using Sliding mode system (ESDS). This estimator is able to eliminate impulsive noise efficiently from time series data. We applied this filter to processing outputs of robot sensors, and it became possible to perform robust environment recognition. ESDS is designed using a theory of variable structure system (VSS) with sliding mode. In short, ESDS is a nonlinear filter. Therefore, it is very difficult to clarify the behavior of the system analytically. Consequentially, we deal with the step function with impulsive noise as an example, and we attempt to eliminate this impulsive noise by keeping the sudden shift of signals. In this case, there is a trade-off between the noise elimination ability and the tracking performance for an input signal. Although ESDS is a nonlinear filter, it has the same trade-off as linear filters such as a low-pass filter. In order to satisfy these two conditions simultaneously, we use two filters whose parameters are independent of each other. Furthermore, in order to repress the adverse affect of impulsive noise in the steady-state, we introduced the boundary layer. Generally, a boundary layer is used so as to inhibit the harmful effect of chattering. Chattering is caused in the sliding mode system when the state of the system vibrates on the switching line of a sliding mode system. By introducing the boundary layer to ESDS, we can repress the adverse effect of impulsive noise in the steady-state. According to these considerations, we clarify the relationship between these characteristics of ESDS and the arbitrary parameters.

In this paper, we propose a simple method to find the optimal rational function, with a fixed denominator, which minimizes an integral of polynomially weighted squared error to given analytic function. Firstly, we present a generalization of the Walsh's theorem. By using the knowledge on the zeros of the fixed denominator, this theorem characterizes the optimal rational function with a system of linear equations on the coefficients of its numerator polynomial. Moreover when the analytic function is specially given as a polynomial, we show that the optimal numerator can be derived without using any numerical integration or any root finding technique. Numerical examples demonstrate the practical applicability of the proposed method.

Telecom- and Signal Relays with gastight plastic sealed housings enables the usage of inert and highly insulating gases. Although plastic sealed housings are used, optimized designs can keep the gas during the entire life of more than 25 years. The application of this technology allows the application of highly insulting gases like SF6 and result in a significant reduction of the relay size as reduced physical dimensions can be applied. With unchanged distances a significantly better dielectric performance can be achieved, without a relevant cost increase. Furthermore the inert switching atmosphere increases the switching characteristics or reduces the consumption of precious metals for the contacts. Even the usage of less precious metals like tungsten or ruthenium might be possible for switching typical telecommunication signals.

Design patterns can be regarded as an approach to encapsulate and reuse good design practices. However, most design patterns are specified using informal text and examples. To obtain all of the benefits of patterns, formal specification and tool support are indispensable. This paper proposes a Design Pattern Specification Language (DPSL) that is both manageable and effective. The DPSL provides software developers with the capability to treat design patterns as concrete design units without lowering abstraction. To demonstrate the usability of our DPSL and its application in design modeling, we have developed a prototype tool that supports the DPSL in UML diagrams. This prototype allows us to demonstrate the tool's support possibilities and the usability of patterns for software development applications.

This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.

In this paper, we first investigate the characteristics of movie contents over the Internet. As in the previous studies, we found the lognormal-distribution well fits the distribution of file size for the whole set of general movie contents. When we specifically focus on the subset that consists of movie trailers, however, it shows different distribution from the lognormal-distribution. Our analysis shows it is similar to an exponential-distribution. We here assume that movie trailers are one of the relevant contents for Contents Delivery Networks (CDN) or Peer-to-Peer (P2P) file exchange communities. We further studies the relationship between playing duration and file size for the movie trailers and we did not find any linear correlation among them. We next consider bandwidth requirements to retrieve movie trailer contents. Our objective is to make it possible for user to view the contents in real-time. Many previous studies investigate bandwidth requirement based only on the file size distribution. In this paper, we analyze the traffic design criteria for CDN or P2P by taking into account both of the results for the file size distribution and the relationship between playing duration and file size for movie trailers. Simulation studies reveal the impact for the bandwidth requirement.

Utilizing a macromodel which calculates the floating gate potential by combining resistances and dependent voltage and current sources, DC transfer characteristics for multi-input neuron MOS inverters and for those in the neuron MOS full adder circuit are simulated both at room temperature and at 77 K. Based on the simulated results, low temperature circuit failures are discussed. Furthermore, circuit design parameter optimization both for low and room temperature operations is described.

It is well known that Orthogonal Frequency Division Multiplexing (OFDM) scheme is robust to frequency selective fading in wireless channels. However, once delayed signals beyond a guard interval of an OFDM symbol are introduced in a channel with large delay spread, inter-symbol interference causes a severe degradation in the transmission performance. In this paper, we propose a novel pre-Fast Fourier Transform (FFT) OFDM adaptive antenna array, which requires only one FFT processor at a receiver, for suppressing such delayed signals. We analytically derive the optimum weights for the beamformer based on the Maximum Signal-to-Noise-and-Interference power Ratio (SNIR) and the Minimum Mean Square Error (MMSE) criteria, respectively. Computer simulation results show its good performance even in a channel where Directions of Arrival (DoAs) of arriving waves are randomly determined.

An efficient performance enhancement scheme using the rotation of signal subspace (RSS) and Toeplitz matrix approximation (TMA) methods to enhance the performance of an adaptive antenna array in DS/CDMA systems is proposed. The basis of RSS is to find a transformation matrix in order to recover the desired complex array covariance matrix from a sampled complex array covariance matrix which is contaminated by an interference-plus-noise component. Also, the objective of TMA is to change the output matrix of RSS into a matrix having the theoretical properties such as Toeplitz structure matrix or a positive semidefinite matrix. Consequently, the proposed scheme using RSS and TMA methods can greatly improve the performance of an adaptive antenna array by reducing the interference-plus-noise effect from the sampled complex array covariance matrix of the pre-correlation received signal vector that is used to calculate a weight vector of an adaptive antenna array. Simulation results demonstrate the effectiveness of the proposed scheme.

This paper describes a novel four-quadrant analog multiplier. It is comprised of two mixed signal circuits, a voltage adder circuit, a voltage divider circuit and a basic multiplier. Its major advantages over the other analog multipliers are: this design has single ended inputs, the geometry of all CMOS transistors are equal, and its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects are analyzed, and the experimental and simulative results that confirm the theoretical analysis are carried out.

Piecewise linear (PWL) circuit modules operating on sigma-delta (ΣΔ) modulated signals and nonlinear signal processors built of these modules are proposed. The proposed module library includes absolute circuits, min/max selectors and negative resistances. Their output signal-to-noise ratio is higher than 50dB when their oversampling ratio is 28. A nonlinear filter and a stochastic resonator are presented as applications of the PWL modules to ΣΔ domain signal processing. The filter is structured with 37% of logic gates consumed by an equivalent filter with a 5-bit parallel signal form.

Micali and Rivest have proposed a transitive signature scheme for an undirected graph, which is suitable for signing data with undirected graph structure. The problem of finding a transitive signature scheme for a directed graph has remained an open problem. In this paper, we propose a transitive signature scheme for a directed tree. Since the directed tree is a special case of the directed graph, the proposed scheme is a partial solution for the open problem. We also show that a transitive signature scheme for the undirected graph can be constructed from a bundling homomorphism. This means that the transitive signature scheme for the undirected graph is closely related with a fail-stop signature scheme.

Our work introduces a speech enhancement algorithm that modifies on-line the spectral representation of degraded speech to approximate the spectral coefficients of high quality speech. The proposed framework is based on the application of Discrete Fourier Transform (DFT) to a large ensemble of clean speech frames and the estimation of parametric, heavy-tail non-Gaussian probability distributions for the spectral magnitude. Each clean spectral band possesses a unique pdf. This is selected according to the smallest Kullback-Leibler divergence between each candidate heavy-tail pdf and the non-parametric pdf of the magnitude of each spectral band of the clean ensemble. The parameters of the distributions are derived by Maximum Likelihood Estimation (MLE). A maximum a-posteriori (MAP) formulation of the degraded spectral bands leads to soft threshold functions, optimally derived from the statistics of each spectral band and effectively reducing white and slowly varying coloured Gaussian noise. We evaluate the new algorithm on the task of improving the quality of speech perception as well as Automatic Speech Recognition (ASR) and demonstrate its robustness at SNRs as low as 0 dB.

An 80 Gbit/s conventional and carrier-suppressed return-to-zero optical time-division multiplexing signal transmission over a 208 km standard single-mode fiber was experimentally demonstrated. This was achieved by using mid-span optical phase conjugation based on four-wave mixing in semiconductor optical amplifiers. In addition, it was confirmed that the transmitted carrier-suppressed return-to-zero optical signal's carrier phase-relation was held.

This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array which enables dynamic and autonomous reconfiguration of the logic circuits. The LSI was completed by successfully introducing two specific features: fully asynchronous logic circuits and a homogeneous structure, only LUTs are used.

A configurable device "PCA-Chip2" implements the concept of Plastic Cell Architecture, which is an extension of programmable logic devices. This paper presents basic design tools for the PCA-Chip2 as the first step to develop the total design environment. Given a C description of a target function, configuration data for PCA-Chip2 is automatically generated by the tools. Trial designs by the tools are also presented to demonstrate the practicability of the proposed approach.

Reconfigurable architectures have been focused for its potential on achieving high performance by reconfiguring special purpose circuits for a target application and its flexibility due to its ability of reconfiguring. We have set our sights on use of a reconfigurable architecture as a general-purpose computer by extending the advantageous properties of the architecture. To achieve the goal, a generalized execution model for reconfigurable architecture is required, so we have proposed an Ideal PARallel Structure (I-PARS) execution model. In the I-PARS execution model, any programs based on its model has no restriction depending on hardware structures based on a specific reconfigurable processor, which makes it easier to develop software. Further, we have proposed a PARS architecture which executes programs based on the I-PARS execution model effectively. The PARS architecture has a large reconfigurable part for highly parallel execution, which utilizes parallelism described on the I-PARS execution model. For effective utilization of the reconfigurable part in the PARS architecture, it has an ability to reconfigure and execute operations simultaneously in one cycle. Further, the PARS architecture supports branch operations to introduce control flow in an execution on the architecture, which makes it possible to skip an execution which does not produce a valid result. In this paper, we introduce the detailed structure of an implemented prototype processor based on the PARS architecture. In the implementation, 420,377 CMOS transistors were used, which was only 3.8% of the number of transistors used in the UltraSPARC-III in logic circuits. Additionally, we evaluated the performance of the prototype processor by using some benchmark programs. From the evaluation results, we found that the prototype processor could achieve nearly the same performance and be implemented with extremely the less number of transistors compared with UltraSPARC-III 750MHz.