The traffic congestion problem in urban areas is worsening since traditional traffic signal control systems cannot provide] efficient traffic regulation. Therefore, dynamic traffic signal control in Intelligent Transportation System (ITS) recently has received increasing attention. This study devised a multi-agent architecture, the Adaptive and Cooperative Traffic light Agent Model (ACTAM), for a decentralized traffic signal control system. The proposed architecture comprises a data storage and communication layer, a traffic regulation factor processing layer, and a decision-making layer. This study focused on utilizing the cooperation of multi-agents and the prediction mechanism of our architecture, the Forecast Module, to forecast future traffic volume in each individual intersection. The Forecast Module is designed to forecast traffic volume in an intersection via multi-agent cooperation by exchanging traffic volume information for adjacent intersections, since vehicles passing through nearby intersections were believed to significantly influence the traffic volume of specific intersections. The proposed architecture can achieve dynamic traffic signal control. Thus, total delay time of the traffic network under ACTAM can be reduced by 37% compared to the conventional fixed sequence traffic signal control strategy. Consequently, traffic congestion in urban areas can be alleviated by adopting ACTAM.

This paper treats multi-way microstrip power dividers composed of multi-step, multi-furcation, and corners. Since the design procedure is founded on the planar circuit approach in combination with the segmentation method, optimization of the circuit configuration can be performed in a reasonable short computation time when applying the Powell's optimization algorithm. Actually, broadband 3- and 4-way power dividers with mitered bends are designed, and fractional bandwidths of about 90% and 100% are realized for the power-split imbalance less than 0.2 dB and the return loss better than -20 dB, respectively. The validity of the design results is confirmed by an EM-simulator (HFSS) and experiments.

One of the main disadvantage of multi-carrier CDMA (MC-CDMA) signals is the high peak power of the transmitted signals which limits their applications. To account for this issue, we provide a simple signal processing for reducing the high crest factor (CF) of MC-CDMA signals. Using this modified MC-CDMA signal, the high CF due to Walsh spreading sequences can be mitigated without explicit side information and degradation in the detection performance.

SFLASH was chosen as one of the final selection of the NESSIE project in 2003. It is one of the most efficient digital signature scheme and is suitable for implementation on memory-constrained devices such as smartcards. Side channel attacks (SCA) are a serious threat to memory-constrained devices. If the implementation on them is careless, the secret key may be revealed. In this paper, we experimentally analyze the effectiveness of a side channel attack on SFLASH. There are two different secret keys for SFLASH, namely the proper secret key (s,t) and the random seed Δ used for the hash function SHA-1. Whereas many papers discussed the security of (s,t), little is known about that of Δ. Steinwandt et al. proposed a theoretical DPA for finding Δ by observing the XOR operations. We propose another DPA on Δ using the addition operation modulo 232, and present an experimental result of the DPA. After obtaining the secret key Δ, the underlying problem of SFLASH can be reduced to the C* problem broken by Patarin. From our simulation, about 1408 pairs of messages and signatures are needed to break SFLASH. Consequently, SHA-1 must be carefully implemented in order to resist SCA on SFLASH.

We present two new parallel algorithms for extending the domain of a UOWHF. The first algorithm is complete binary tree based construction and has less key length expansion than Sarkar's construction which is the previously best known complete binary tree based construction. But only disadvantage is that here we need more key length expansion than that of Shoup's sequential algorithm. But it is not too large as in all practical situations we need just two more masks than Shoup's. Our second algorithm is based on non-complete l-ary tree and has the same optimal key length expansion as Shoup's which has the most efficient key length expansion known so far. Using the recent result, we can also prove that the key length expansion of this algorithm and Shoup's sequential algorithm are the minimum possible for any algorithms in a large class of "natural" domain extending algorithms. But its parallelizability performance is less efficient than complete tree based constructions. However if l is getting larger, then the parallelizability of the construction is also getting near to that of complete tree based constructions. We also give a sufficient condition for valid domain extension in sequential domain extension.

We consider delivering interactive dramas. A viewer interacts with a contents provider by answering multiple-choice questions and the answers to these questions influence the plot of delivered story. All possible plots can be represented by a directed graph such that every plot corresponds to some path of the graph. A delivery should be controlled according to the directed graph such that each viewer's history of answered choices forms a path of the graph. On the other hand, because some character of a viewer is known to a contents provider from his history of choices, a viewer tries to prevent even a contents provider from linking choices made by him. In this paper, we introduce unlinkable delivery for an interactive drama and propose such a delivery system for interactive dramas that viewer's choices are unlinkable and delivery is controlled according to the directed graph.

An inverse-RZ modulation scheme for dense WDM systems is proposed. Inverse-RZ signals have tolerances to chromatic dispersion and optical bandwidth limitation. The strongly pre-filtered inverse-RZ signals can be adapted to ultra-dense WDM systems, in which the spectral efficiencies are over 1.0 b/s/Hz. We have confirmed the error-free transmission of pre-filtered and co-polarized 40-Gb/s inverse-RZ signals where the channel intervals were 37.5 GHz.

The Public Key Infrastructure (PKI) technology is very important to support the electronic commerce and digital communications on existing networks. The Online Certificate Status Protocol (OCSP) is the standard protocol for retrieving certificate revocation information in the PKI. To minimize the damages caused by OCSP responder's private key exposure, a distributed OCSP composed of multiple responders is needed. This paper presents a new distributed OCSP with a single public key by using key-insulated signature scheme. In proposed distributed OCSP, each responder has the different private key, but corresponding public key remains fixed. Therefore the user simply obtains and stores one certificate, and can verify any responses by using a single public key.

This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.

In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

We present a new approach to the power modeling of synthesizable soft macros, which uses the characteristics of individual input signals for high accuracy. We also present the parameterized power model, developed using the proposed approach, which can relieve us from the power characterization for all possible macro sizes. Extensive experiments illustrate that the proposed approaches exhibit the overall modeling errors below 4.24% and 4.71% for benchmark macros before and after parameterization, when compared with the results of gate-level analysis.

The partial projection filter gives optimal signal restoration in the presence of both the signal space and the observation space noises. In this paper, the filter has been characterized from the point of view of its signal restoration and noise suppression capabilities. The filter is shown to suppress the noise component in the restored signal while retaining the signal component, thus maximizing the signal-to-noise ratio. Further, a digital implementation of the filter is presented in matrix form in contrast to its original operator based derivation, for practical applications.

A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(log2n+1)+3log2m) Read/Write operations for a 2nm-bit memory, where n and m are the address width and data width, respectively. Also, the algorithms can verify 100% of the inter-port and intra-port signal misplaced faults of the address, data input, and data output ports.

This paper presents CrtSmile--a CAD tool for the automatic extraction of layout-dependent substrate effects for RF MOSFET modeling. CrtSmile incorporates a new scalable substrate model, which depends not only on the geometric layout information of a transistor (the number of gate fingers, finger width, channel length and bulk contact location), but also on the transistor layout and bulk patterns. We show that this model is simple to extract and has good agreement with measured data for a 0.35 µm CMOS process. CrtSmile reads in the layout information of RF transistors in the CIF/GDSII format, performs a pattern-based layout extraction to recognize the transistor layout and bulk patterns. A scalable layout-dependent substrate model is automatically generated and attached to the standard BSIM3 device model as a sub-circuit for use in circuit simulation. A low noise amplifier is evaluated with the proposed CrtSmile tool, showing the importance of layout effects for RF transistor substrate modeling.

This paper proposes an independent control for parallel-connected multiple uninterruptible power supply (UPS) systems based upon a very simple control scheme. Here, the amplitude and phase angle of the output voltage are the controllable variables. With the only measurement of the output current, the active and reactive components are calculated to define the control variables. The entire system including the equations for the circuit, control and voltage limiters is well represented by a small-signal model, in which the computation of its eigenvalues constitutes the stability proof of the system. The root locus diagram gives an overall panorama of the system performance as a function of a certain gain and it aims to aid the further understanding and the design of the control. The experimental verification is carried out using a mere proportional-integral control scheme, which is a special case of the general control equation used in the theoretical analysis. For some situations, experiments show a flow of lateral current between UPS's, which causes an unbalanced current distribution. By increasing the proportional gain of the control equation for the output voltage amplitude, the lateral current can be substantially suppressed with a consequent improvement of the load sharing. Experimental results under various conditions show excellent results in terms of synchronization, load sharing and stability for three distinct output rating UPS's connected in parallel.

In 2000, Wang et al. proposed a (t,n) threshold signature scheme with (k,l) threshold shared verification, and a (t,n) threshold authenticated encryption scheme with (k,l) threshold shared verification. Later, Tseng et al. mounted some attacks against Wang et al.'s schemes. At the same, they also presented the improvements. In this paper, we first point out that Tseng et al.'s attacks are actually invalid due to their misunderstanding of Wang et al.'s Schemes. Then, we show that both Wang et al.'s schemes and Tseng et al.'s improvements are indeed insecure by demonstrating several effective attacks.

This paper presents a new method for blind source separation by exploiting phase and frequency redundancy of cyclostationary signals in a complementary way. It requires a weaker separation condition than those methods which only exploit the phase diversity or the frequency diversity of the source signals. The separation criterion is to diagonalize a polynomial matrix whose coefficient matrices consist of the correlation and cyclic correlation matrices, at time delay τ= 0, of multiple measurements. An algorithm is proposed to perform the blind source separation. Computer simulation results illustrate the performance of the new algorithm in comparison with the existing ones.

The problem of signal restoration in the presence of observation space noise has been tackled extensively. However, restoration of degraded signals in the presence of signal space noise leads to considerable complexity because it becomes difficult to distinguish between the original signal and the noise. In this paper, a partial projection filter has been devised for the restoration of signals degraded by both the signal space and the observation space noises. A closed form of the proposed filter has been derived and its performance has been verified experimentally.

This paper presents a novel algorithm for crosspoint assignment (CPA) that takes into consideration crosstalk noise and shielding effects in deep sub-micron design. We introduce a conditional constraint which is imposed on a sensitive net-pair to detach one net from the other or to put another insensitive net between them for shielding. We provide two algorithms which can handle the conditional constraint: One is based on an ILP, which outputs an exact optimum solution. The other is a fast heuristics whose time complexity is O(n2 log n), where n is the number of pins. In experiments, we tested these algorithms for industrial examples. The results showed that the conditional constraint for shielding released algorithms from a tight space of feasible assignments. Our heuristics ran quickly and attained near optimum solutions.

We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.