This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.

Davidson's scheme utilizes the order of basic blocks to embed a digital signature in a computer program. To preserve the function of the original program, additional jump instructions are inserted. This involves some overhead in both size and performance. In our implementation, the increase in size was between 9% and 24%. The performance of benchmark programs was 86-102% of the original.

Synchronous Gaussian code-division multiple access (CDMA) systems employing group-orthogonal signature waveforms are proposed and analyzed. All users in the system are divided into groups of users. The signature waveforms are constructed such that all the signature waveforms in one group are orthogonal to all the signature waveforms used in all other groups. This construction of signature waveforms ensures that there is no inter-group interference (i.e., among users in different groups), but at the expense of having intra-group interference (i.e., among users in the same group). However, by choosing a small size for each group, the intra-group interference can be effectively handled by a low-complexity, optimal (or suboptimal) multiuser detector. It is shown that a significant improvement in the system capacity can be achieved by the proposed technique over the conventional one that uses signature waveforms constructed from Welch-bound-equality (WBE) sequences. In particular, it is demonstrated that, while the conventional system's error performance is very sensitive to even small amount of overload, the proposed system with an appropriate design of signature waveforms can achieve a much higher overload (up to 300% as shown in the paper) with an excellent error performance.

We propose an estimation method of crosstalk noise for generic RC trees. The proposed method derives an analytic waveform of crosstalk noise in a 2-π equivalent circuit. The peak voltage is calculated from the closed-form expression. We also develop a transformation method from generic RC trees with branches into the 2-π model circuit. The proposed method can hence estimate crosstalk noise for any RC trees. Our estimation method is evaluated in a 0.13 µm technology. The peak noise of two partially-coupled interconnects is estimated with the average error of 11%. Our method transforms generic RC interconnects with branches into the 2-π model with 14% error on average.

We consider the routing and wavelength assignment (RWA) problem for large-scale WDM optical networks where each transmission request is served by an all-optical lightpath without wavelength conversion. Two heuristic RWA algorithms are proposed in order to minimize the number of wavelengths required for a given set of connection requests. The proposed algorithms are evaluated and compared with the existing algorithms for two realistic networks constructed based on the locations of major cities in Ibaraki Prefecture and those in Kanto District in Japan.

Delta-sigma modulators (DSMs) are commonly use in high-resolution analog-to-digital converters, and band-pass delta-sigma modulators have recently been used to convert IF signals into digital signals. In particular, a quadrature band-pass delta-sigma modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. The current paper proposes a second-order three-bit quadrature band-pass delta-sigma modulator that can achieve a lower power consumption and better performance with a similar die size to a conventional fourth-order quadrature band-pass delta-sigma modulator (QBPDSM). The proposed system is integrated using CMOS 0.35 µm, double-poly, four-metal technology. The system operates at 13 MHz and can digitize a 200 kHz bandwidth signal centered at 4.875 MHz with an SNR of 85 dB. The power consumption is 35 mW at 3.3 V and 38 mW at 5 V, and the die size is 21.9 mm2.

We analyze the timing design methodology for testing chips using a multiple-clock domain scheme. We especially focus on the layout design of the design-for-test (DFT) circuits and the clock network. First, we demonstrate the built-in-self-testing (BIST) scheme for multiple-clock domains. Then, we discuss the layout method that achieves a low clock-skew between different clock domains with a small modification of the original user logic layout. Finally, we evaluate the fault coverage of our large ASIC chips designed using our new methodology. The short design period and high fault coverage of our methodology are confirmed using actual industrial designs. We introduce a viable approach for industrial designs because designers don't have to pay much attention to DFT. Our approach also provides designers with an easy method for LSI debugging and diagnostics.

This paper presents the summarized achievements of "Study Group on Software Technology for Radio Equipment" held at TELEC from April 2000 to March 2003. The Study Group specified the essential issues on Software Defined Radio (SDR), and discussed desirable methods to evaluate conformity to technical regulations in radios that can change RF characteristics only by changing software. The biggest objective in SDR is to build the architecture to allow users to install software exclusively in the combination of hardware and software that have passed the certification test. The Study Group has reached a solution by introducing the idea of "tally." This paper explains the concept of tally, and proposes two types of systems to use tallies in checking adaptability in combinations of hardware and software.

This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistor-level circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35 µm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11-20% and power dissipation decreases to 42-62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance.

In an LSI design process, Engineering Change Orders (ECO's) are often given even after the layout process. This letter presents an approach to change the design to satisfy the new specification with ECO's by employing an error diagnosis technique. Our approach performs incremental synthesis using spare cells embedded on the original layout. Experimental results show that applying the error diagnosis technique to incremental synthesis is effective to suppress increase in delay time caused by ECO's.

The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.

The power dissipation at the off-chip bus has become a significant part of the overall power dissipation in micro-processor based digital systems. This paper presents irredundant address bus encoding methods which reduce signal transitions on the instruction address buses by using adaptive codebook methods. These methods are based on the temporal locality and spatial locality of instruction address. Since applications tend to JUMP/BRANCH to limited sets of addresses, proposed encoding methods assign the least signal transition codes to the addresses of JUMP/BRANCH operations in the past. In addition, our methods can be easily applicable for conventional digital systems since they are irredundant encoding methods. Our encoding methods reduce the signal transitions on the instruction address buses, which results in the reduction of total power dissipation of digital systems. Experimental results show that our methods can reduce the signal transition by an average of 88%.

This paper presents a variable pipeline depth processor, which can dynamically adjust its pipeline depth and operating voltage at run-time, we call dynamic pipeline and voltage scaling (DPVS), depending on the workload characteristics under timing constraints. The advantage of adjusting pipeline depth is that it can eliminate the useless energy dissipation of the additional stalls, or NOPs and wrong-path instructions which would increase as the pipeline depth grow deeper in excess of the inherent parallelism. Although dynamic voltage scaling (DVS) is a very effective technique in itself for reducing energy dissipation, lowering supply voltage also causes performance degradation. By combining with dynamic pipeline scaling (DPS), it would be possible to retain performance at required level while reducing energy dissipation much further. Experimental results show the effectiveness of our DPVS approach for a variety of benchmarks, reducing total energy dissipation by up to 64.90% with an average of 27.42% without any effect on performance, compared with a processor using only DVS.

As the CMOS technology enters the very deep submicron era, inter-wire coupling capacitance becomes the dominant part of load capacitance. The coupling effects have brought new challenges to routing algorithms on both delay estimation and optimization. In this paper, we propose a timing-driven global routing algorithm with consideration of coupling effects. Our two-phase algorithm based on timing-relax method includes a heuristic Steiner tree algorithm to guarantee the timing performance of the initial solution and an optimization algorithm based on coupling-effect-transference. Experimental results are given to demonstrate the efficiency and accuracy of the algorithm.

One of the important topics of watermarking technique is a robustness against geometrical transformations. In the previous schemes, a template matching is performed or an additional signal is embedded for the recovery of a synchronization loss. However, the former requires the original template, and the latter degrades the quality of image because both a watermark and a synchronization signal must be embedded. In the proposed scheme only a synchronization signal is embedded for the recovery of both a watermark and a synchronization loss. Then the embedded information depends on the distance between two embedded signal positions. The distance is not changed seriously by random geometrical transformations like StirMark attack unless the embedded signal is disturbed. Therefore, a watermark can be extracted correctly from such geometrically transformed image if the synchronization signal can be recovered.

A flexible symbol-timing synchronization met-hod is a one that uses a common sampling clock to find synchronization points for radio communication systems that have different symbol rates. This method estimates synchronization points from state patterns calculated using the symbol rate, sampling clock, and number of observed symbols. Decreasing the number of state patterns is one of best ways to reduce the amount of device resources needed to store the patterns. In this paper, we propose a new pattern generation method in which the number of generated patterns does not increase when the sampling clocks of the communications systems are different. To show the feasibility of this method for symbol-timing synchronization, we analyzed a relationship between the number of samples and the number of state patterns and calculated the BER (bit error rate) in AWGN (additive white Gaussian noise) and one-path flat Rayleigh fading environments by computer simulation.

Asynchronous controllers effectively control high concurrence of datapath operations for high speed. Signal Transition Graphs (STGs) can effectively represent these concurrent events. However, highly concurrent STGs cause the state explosion problem in asynchronous synthesis tools. Many small but highly concurrent STGs cannot be synthesized to obtain control circuits. Moreover, STGs also lead to some control-time overhead of the four-phase handshake protocol. In this paper, we propose a method for deriving the serial control nodes from Control Data Flow Graphs (CDFGs) such that the concurrence of datapath operations is still preserved. The STGs derived from the serialized control nodes are serial STGs which are simpler for synthesis than the concurrent STGs. We also propose an implementation using these serialized controllers to generate local clocks at any necessary times. The implementation results in very small control-time overhead. The experimental results show that the number of synthesis states is proportional to the number of control signals, and the circuits with satisfiable small control-time overhead are obtained.

This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.

A mathematical expression for the received signal power in a severe frequency-selective fading channel is derived. Using the derived expression, the signal power distributions are obtained by Monte-Carlo simulation and compared with the Nakagami m-power distribution. It is found that the power distribution matches well with the Nakagami m-power distribution when the multipath channel has a uniform power delay profile.

In this paper, we consider the problem of bearing estimation for spatially distributed sources in unknown spatially-correlated noise. Assumed that the noise covariance matrix is centro-Hermitian, a differential denoising scheme is developed. Combined it with the classic DSPE algorithm, a differential denoising estimator is formulated. Its modified version is also derived. Exactly, the differential processing is first imposed on the covariance matrix of array outputs. The resulting differential signal subspace (DSS) is then utilized to weight array outputs. The noise components orthogonal to DSS are eliminated. Based on eigenvalue decomposition of the covariance matrix of weighted array outputs, the DSPE null spectrum is constructed. The asymptotic performance of the proposed bearing estimator is evaluated in a closed form. Moreover, in order to improve the performance of bearing estimation in case of low signal-to-noise ratio, a modified differential denoising estimator is proposed. Simulation results show the effectiveness of the proposed estimators under the low SNR case. The impacts of angular spread and number of sensors are also investigated.