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1601-1620hit(2667hit)

  • A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit

    Hideho ARAKIDA  Masafumi TAKAHASHI  Yoshiro TSUBOI  Tsuyoshi NISHIKAWA  Hideaki YAMAMOTO  Toshihide FUJIYOSHI  Yoshiyuki KITASHO  Yasuyuki UEDA  Tetsuya FUJITA  

     
    PAPER

      Vol:
    E87-C No:4
      Page(s):
    475-481

    We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.

  • Inverse Problem Techniques for the Design of Photonic Crystals

    Martin BURGER  Stanley J. OSHER  Eli YABLONOVITCH  

     
    INVITED PAPER

      Vol:
    E87-C No:3
      Page(s):
    258-265

    This paper provides a review on the optimal design of photonic bandgap structures by inverse problem techniques. An overview of inverse problems techniques is given, with a special focus on topology design methods. A review of first applications of inverse problems techniques to photonic bandgap structures and waveguides is given, as well as some model problems, which provide a deeper insight into the structure of the optimal design problems.

  • Preemptive System-on-Chip Test Scheduling

    Erik LARSSON  Hideo FUJIWARA  

     
    PAPER-SoC Testing

      Vol:
    E87-D No:3
      Page(s):
    620-629

    In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

  • Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions

    Kiyoharu HAMAGUCHI  

     
    LETTER

      Vol:
    E87-D No:3
      Page(s):
    637-641

    This letter handles symbolic simulation for high-level hardware design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics.

  • A DFT Selection Method for Reducing Test Application Time of System-on-Chips

    Masahide MIYAZAKI  Toshinori HOSOKAWA  Hiroshi DATE  Michiaki MURAOKA  Hideo FUJIWARA  

     
    PAPER-SoC Testing

      Vol:
    E87-D No:3
      Page(s):
    609-619

    This paper proposes an SoC test architecture generation framework. It contains a database, which stores the test cost information of several DFTs for every core, and a DFT selection part which performs DFT selection for minimizing the test application time using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm that solves this problem is proposed. Experimental results show that bottlenecks in test application time when using a single DFT method for all cores in an SoC is reduced by performing DFT selection from two types of DFTs. As a result, the whole test application time is drastically shortened.

  • On Signals in Asynchronous Cellular Spaces

    Susumu ADACHI  Jia LEE  Ferdinand PEPER  

     
    PAPER

      Vol:
    E87-D No:3
      Page(s):
    657-668

    This paper studies the propagation and crossing of signals in cellular automata whose cells are updated at random times. The signals considered consist of a core part, surrounded by an insulating sheath that is missing at the side of the core that corresponds to the direction into which the signal moves. We study two types of signals: (1) signals by which the sheath at the left and right sides of the core advance first in a propagation step, followed by the core, and (2) signals by which the core advances first, followed by the sheath at its left and right sides. These types naturally arise in, respectively, Moore neighborhood cellular automata with semi-totalistic rules and von Neumann neighborhood cellular automata with symmetric transition rules. The type of a signal has a profound impact on the way signals cross each other, as we show by the construction of one signal of each type. The results we obtained should be of assistance in constructing asynchronous circuits on asynchronous cellular automata.

  • Network Design for Multi-Layered Photonic IP Networks Considering IP Traffic Growth

    Shigeru KANEDA  Tomohiko UYEMATSU  Naohide NAGATSU  Ken-ichi SATO  

     
    PAPER-Internet

      Vol:
    E87-B No:2
      Page(s):
    302-309

    In order to transport an ever-increasing amount of IP traffic effectively, Photonic IP networks that employ wavelength routing and Layer 3 cut-through are very important. This paper proposes a new network design algorithm that minimizes the network cost considering IP traffic growth for multi-layered photonic IP networks that comprise electrical label switched paths (LSPs) and optical LSPs. We evaluate the network cost obtained from the developed network design algorithm that considers IP traffic growth and compare it to the results obtained from a static zero-based algorithm. The static zero-based algorithm does not take into account the history of progressive past IP traffic changes/growth until that time. The results show that our proposed algorithm is very effective; the cost increase from the cost obtained using the zero-based algorithm is marginal. The algorithm developed herein enables effective multi-layered photonic IP network design that can be applied to practical networks where IP traffic changes/increases progressively and that can be used for long term network provisioning.

  • Binary-Quantized Diffusion Systems and Their Filtering Effect on Sigma-Delta Modulated Signals

    Daisuke HAMANO  Hisato FUJISAKA  Mititada MORISUE  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E87-A No:2
      Page(s):
    433-443

    We propose binary-quantized and spatio-temporally discretized network models of linear diffusion systems and investigate their filtering effect on single-bit sigma-delta (ΣΔ) modulated signals. The network consists of only one kind of elements that add ΣΔ modulated signals and quantize the sum in the form of single-bit signal. A basic one-dimensional network is constructed first. Then, the network is extended into two dimensions. These networks have characteristics equivalent to those of linear diffusion systems in both time and frequency domains. In addition, network noise caused by the quantization in the elements contains low-level low-frequency components and high-level high-frequency components. Therefore, the proposed networks have possibility to be used as signal propagation and diffusion media of ΣΔ domain filters.

  • A Novel Contour Description with Expansion Ability Using Extended Fractal Interpolation Functions

    Satoshi UEMURA  Miki HASEYAMA  Hideo KITAJIMA  

     
    PAPER-Image Processing, Image Pattern Recognition

      Vol:
    E87-D No:2
      Page(s):
    453-462

    In this paper, a novel description method of the contour of a shape using extended fractal interpolation functions (EFIFs) is presented. Although the scope of application of traditional FIFs has been limited to cases in which a given signal is represented by a single-valued function, the EFIFs derived by the introduction of a new parameter can describe a multiple-valued signal such as the contour of a shape with a high level of accuracy. Furthermore, the proposed description method possesses the useful property that once a given contour has been modeled by the proposed description method, the shape can be easily expanded at an arbitrary expansion rate. Experimental results show the effectiveness and usefulness of the proposed description method for representing contours.

  • A Formal Treatment of Non-repudiation Protocols

    Satoshi HADA  

     
    PAPER-Information Security

      Vol:
    E87-A No:2
      Page(s):
    461-470

    Non-repudiation is a basic security requirement for electronic business applications to protect against a sender's false denial of having created and sent a message. Typically non-repudiation protocols are constructed based on digital signatures. However, there has been no theoretical treatment of such non-repudiation protocols. In this paper, we provide a formal security definition of non-repudiation protocols and analyze the security of a signature-based protocol. Our security definition and analysis are based on Canetti's framework of universally composable security.

  • Comment on Traceability Analysis on Chaum Blind Signature Scheme

    Narn-Yih LEE  Chien-Nan WU  

     
    LETTER-Information Security

      Vol:
    E87-A No:2
      Page(s):
    511-512

    In 1983, Chaum first introduced the concept of blind signature. In 2003, Hwang, Lee and Lai pointed out that the Chaum scheme cannot meet the untraceability property of the blind signature scheme. This letter will demonstrate that Hwang et al.'s claim is incorrect and the Chaum blind signature scheme still keeps the untraceability property.

  • Efficient Threshold Signer-Ambiguous Signatures from Variety of Keys

    Masayuki ABE  Miyako OHKUBO  Koutarou SUZUKI  

     
    PAPER-Information Security

      Vol:
    E87-A No:2
      Page(s):
    471-479

    This paper presents an efficient and generic solution in the following scenario: There are n independent people using variety of signature schemes such as DSS, RSA, Schnorr, and so on, and a subset of them attempts to sign a document without being identified which subset they are. This is a generalized scenario of the Ring Signatures by Rivest, Shamir and Tauman, whose original scenario limits the subset to be a single person and the base signature scheme to be RSA/Rabin schemes. Our scheme allows any signature schemes based on sigma-protocols and claw-free permutations. It also offers shorter signatures and less computation compared to known generic construction. The security is argued in the random oracle model as well as previous schemes and shows that our scheme achieves reduction cost linear in the number of hash queries while it is square for previous generic constructions.

  • A Design of Neural Signal Sensing LSI with Multi-Input-Channels

    Takeshi YOSHIDA  Takayuki MASHIMO  Miho AKAGI  Atsushi IWATA  Masayuki YOSHIDA  Kazumasa UEMATSU  

     
    PAPER

      Vol:
    E87-A No:2
      Page(s):
    376-383

    A neural-signal sensing system with multi-input-channels was designed utilizing a new chopper amplifier with direct connected to a multiplexer. The proposed system consists of multiplexers, chopper amplifiers, a multi-mode analog-to-digital converter (ADC), and a wireless transmitter. It enables to measure 50-channel signals at the same time, which are selected out of 100 channels to detect useful information. The test chip including 10-channel-inputs chopper-amplifier and multi-mode ADC, that was designed and fabricated with a mixed signal 0.35-µm CMOS technology. Utilizing the proposed direct chopper input scheme and the shared chopper amplifier, the circuits was designed with a small area of 9.4 mm2. High accuracy channel selecting and multiplexing operations were confirmed, and an equivalent input noise of 10-nV/root-Hz was obtained with test chip measurements. Power dissipation of the chopper amplifier and the ADC were 6.0-mW and 2.5-mW at a 3-V supply voltage, respectively.

  • A Construction of Public Key Cryptosystem for Realizing Ciphertext of Size 100 Bit and Digital Signature Scheme

    Masao KASAHARA  Ryuichi SAKAI  

     
    PAPER-Asymmetric Cipher

      Vol:
    E87-A No:1
      Page(s):
    102-109

    Extensive studies have been made of the public key cryptosystems based on multivariate polynomials. However most of the proposed public key cryptosystems of rate 1.0 based on multivariate polynomials, are proved not secure. In this paper, we propose several types of new constructions of public key cryptosystems based on two classes of randomly generated simultaneous equations, namely, a class based on bijective transformation and another class based on random transformation. One of the features of the proposed cryptosystems is that the sets of random simultaneous equations significantly improve the utilization factor of the transformation. We show an example of the proposed cryptosystem whose size of the ciphertext is only 100 bits.

  • Improved CMOS Microwave Linearity Based on the Modified Large-Signal BSIM Model

    Hong-Hsin LAI  Chao-Chih HSIAO  Chin-Wei KUO  Yi-Jen CHAN  Takuro SATO  

     
    PAPER-Semiconductor Materials and Devices

      Vol:
    E87-C No:1
      Page(s):
    76-80

    A modified 0.35 µm gate-length MOSFET large-signal microwave device model, based on the widely used BSIM3 model, is presented in this report. This large-signal microwave model includes a BSIM3 model together with the passive components required to fit the device dc and microwave characteristics over a wide range of biasing points and frequency operation. In this report, we propose a methodology to improve the device microwave linearity by controlling a suitable biasing condition, which is based on the predictions of this modified CMOS large-signal model. The input IM3 enhances more than 10 dB at a 2.4 GHz operation. Furthermore, the adjacent channel power ratio also improves 7.5 dB with proper choosing device dc bias.

  • A Generalization of Binary Zero-Correlation Zone Sequence Sets Constructed from Hadamard Matrices

    Takafumi HAYASHI  

     
    LETTER-Coding Theory

      Vol:
    E87-A No:1
      Page(s):
    286-291

    The present paper introduces a new construction of a class of binary sequence set having a zero-correlation zone (hereafter binary zcz sequence set). The cross-correlation function and the side-lobe of the auto-correlation function of the proposed sequence set is zero for the phase shifts within the zero-correlation zone. This paper shows that such a construction generates a binary zcz sequence set from an arbitrary pair of Hadamard matrices of common size. Since the proposed sequence construction generates a sequence set from an arbitrary pair of Hadamard matrices, many more types of sequence sets can be generated by the proposed sequence construction than is possible by a sequence construction that generates sequence sets from a single arbitrary Hadamard matrix.

  • Improving the Capacity of Synchronous CDMA Systems with Group-Orthogonal Signature Waveforms

    Ha H. NGUYEN  

     
    PAPER-Wireless Communication Technology

      Vol:
    E87-B No:1
      Page(s):
    68-78

    Synchronous Gaussian code-division multiple access (CDMA) systems employing group-orthogonal signature waveforms are proposed and analyzed. All users in the system are divided into groups of users. The signature waveforms are constructed such that all the signature waveforms in one group are orthogonal to all the signature waveforms used in all other groups. This construction of signature waveforms ensures that there is no inter-group interference (i.e., among users in different groups), but at the expense of having intra-group interference (i.e., among users in the same group). However, by choosing a small size for each group, the intra-group interference can be effectively handled by a low-complexity, optimal (or suboptimal) multiuser detector. It is shown that a significant improvement in the system capacity can be achieved by the proposed technique over the conventional one that uses signature waveforms constructed from Welch-bound-equality (WBE) sequences. In particular, it is demonstrated that, while the conventional system's error performance is very sensitive to even small amount of overload, the proposed system with an appropriate design of signature waveforms can achieve a much higher overload (up to 300% as shown in the paper) with an excellent error performance.

  • Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA

    Yuya MATSUMOTO  Yuichi TANJI  Mamoru TANAKA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E87-A No:1
      Page(s):
    251-257

    This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.

  • 1-out-of-n Signatures from a Variety of Keys

    Masayuki ABE  Miyako OHKUBO  Koutarou SUZUKI  

     
    PAPER-Asymmetric Cipher

      Vol:
    E87-A No:1
      Page(s):
    131-140

    This paper addresses how to use public-keys of several different signature schemes to generate 1-out-of-n signatures. Previously known constructions are for either RSA-type keys only or DL-type keys only. We present a widely applicable method to construct a 1-out-of-n signature scheme that allows mixture use of different flavors of keys at the same time. The resulting scheme is more efficient than previous schemes even if it is used only with a single type of keys. With all DL-type keys, it yields shorter signatures than the ones of the previously known scheme based on the witness indistinguishable proofs by Cramer, et al. With all RSA-type keys, it reduces both computational and storage costs compared to that of the Ring signatures by Rivest, et al.

  • A Distributed Sign-and-Encryption for Anonymity

    DongJin KWAK  SangJae MOON  

     
    LETTER

      Vol:
    E87-A No:1
      Page(s):
    228-230

    Distributed signcryption is specifically designed for distributing a signcrypted message to a designated group. As such, it can not be used in anonymous communication. Accordingly, the current study adds an anonymity property to distributed signcryption that results in almost the same computational load as regards the modular arithmetic. Therefore, the new scheme is more efficient than the expansion for anonymity in, and has potential applications in electronic commerce.

1601-1620hit(2667hit)