An automated synthesis for analog computational circuits in transistor-level configuration is presented. A cell-based structure is introduced to place moderate constraints on the MOSFET circuit topology. Even though each cell has a simple structure that consists of one current path with four transistors, common analog building blocks can be implemented using combinations of the cells. A genetic algorithm is applied to search circuit topologies and transistor sizes that satisfy given specifications. Synthesis capabilities are demonstrated through examples of three types of computational circuits; absolute value, squaring, and cubing functions by using computer simulations and real hardware.

The asymptotic Elias upper bound of codes designed for Hamming distance is well known. Piret and Ericsson have extended this bound for codes over symmetric PSK signal sets with Euclidean distance and for codes over signal sets that form a group, with general distance function respectively. The tightness of these bounds depend on a choice of a probability distribution, and finding the distribution (optimum distribution) that leads to the tightest bound is difficult in general. In this paper we point out that these bounds are valid for codes over the wider class of distance-uniform signal sets (a signal set is referred to be distance-uniform if the Euclidean distance distribution is same from any point of the signal set). We show that optimum distributions can be found for (i) simplex signal sets, (ii) Hamming spaces and (iii) biorthogonal signal set. The classical Elias bound for arbitrary alphabet size is shown to be obtainable by specializing the extended bound to simplex signal sets with optimum distribution. We also verify Piret's conjecture for codes over 5-PSK signal set.

Jan and Tseng, in 1999, proposed two efficient digital signature schemes with subliminal channels. However, we show that a malicious subliminal receiver can forge subliminal messages that will be accepted by other subliminal receivers in Jan and Tseng's two schemes. Moreover, we also present a modification of Jan and Tseng's schemes to repair the security flaw.

This paper discusses two types of polyphase sequence sets, which will successfully provide CDMA systems without co-channel interference. One is a type of ZCZ sets, whose periodic auto-correlation functions take zero at continuous shifts on both side of the zero-shift, and periodic cross-ones also take zero at the continuous shifts and the zero-shift. The other is a new type of sets consisting of some subsets of polyphase sequences with zero cross-correlation zone, called ZCCZ sets, whose periodic cross-correlation functions among different subsets have take zero at continuous shifts on both side of the zero-shift including the zero-shift. The former can achieve a mathematical bound, and the latter can have large size.

We propose a new multiple access communication system based on finite field wavelet spread signature (FFWSS). In addition to the function of frequency diversity and multiple access, which are typically provided by traditional spreading codes, the FFWSS spreads data symbols in time, resulting in robustness against frequency selective slow fading. Using the FFWSS to spread a data symbol so that it is overlapped with neighboring symbols, a FFWSS-CDMA system is developed. It is observed that the ratio of the maximum nontrivial value of periodic correlation function to the code length of FFWSS is the same as that of a Sidelnikov sequence. Using RAKE-based receivers, simulation results show that the proposed FFWSS-CDMA system yields lower bit error rate (BER) than conventional DS-CDMA and MT-CDMA systems in multipath fading channels.

A great deal of effort has been spent to develop strategies for allocation of resources in DS-CDMA systems in order to mitigate effects of interference between users. Here, the choice of spreading sequences and appropriate power allocation play a crucial role. When developing such strategies, CDMA system designers need to ensure that each user meets its quality-of-service requirement expressed in terms of the signal-to-interference+noise ratio. We say that a set of users is admissible in a CDMA system if one can assign sequences to the users and control their power so that all users meet their quality-of-service requirements. In [1], the problem of admissibility in a synchronous CDMA channel was solved. However, since the simplistic setting of perfect symbol synchronism rarely holds in practice, there is a strong need for investigating asynchronous CDMA channels. In this paper, we consider a K-user asynchronous CDMA channel with processing gain N and identical performance requirements for all users assuming chip synchronism. We solve the problem of admissibility of the users in such a channel if N K, and identify optimal sequences. We also show that constant power allocation is optimal. Results obtained in this paper give valuable insights into the limits of asynchronous CDMA systems.

This paper studies the optimization of signature waveforms and power allocation for synchronous code-division multiple access (CDMA) systems under the root-mean-square (RMS) bandwidth constraint. The optimization is considered for two types of receivers, namely the conventional matched filter (MF) receiver and the minimum mean-square error (MMSE) receiver. For both cases, the optimization criterion is to maximize the average signal to interference ratios (SIRs) at the receivers' outputs. For a given RMS bandwidth constraint and an arbitrary power allocation scheme, a procedure to obtain the optimal signature waveforms is provided. Based on this procedure, it is then shown that the optimal power allocation is achieved when all the received powers are equal. With the optimal power allocation, solutions for the optimal signature waveforms are presented and discussed in detail. It is also demonstrated that, compared to the previously obtained Welch-bound-equality (WBE) signature waveforms, the proposed signature waveforms can significantly improve the user performance.

This paper proposes a new blind algorithm effective for multiuser detection with an adaptive array antenna. The conventional blind algorithm, known as the Constant Modulus Algorithm (CMA), has two major drawbacks: (i) the convergence speed is not sufficiently fast for usual applications in mobile communications, and (ii) the algorithm is very likely to lock on the path with the largest received power, which means the signal with the second largest power can hardly be extracted. This paper introduces the Recursive Least Squares algorithm for CMA (RLS-CMA) in order to speed the convergence up, and additionally introduces the concept of the orthogonal projection into CMA so as to extract signals with weak power. The proposed CMA with Orthogonal Projection (CMA-OP) sequentially calculates the weight vector of each user under a constraint that the weight vector should be orthogonal to the estimated array response vectors of previously extracted users. Computer simulations demonstrate that the proposed scheme can operate properly in the Rayleigh fading channels under the two-user condition.

In an order-specified multisignature scheme, one can verify not only a set of signers who have signed the message but also its signing order. Though we have seen several schemes with such properties proposed, none of them is given the security proof against active adversaries. The scheme can be easily modified to be an order-specified multisignature scheme, but still has the restriction that the possible signing orders are only ones of the type of serial signing. In this paper, we propose the first order-specified multisignature scheme, which is shown to be secure against adaptive chosen-message insider attacks in the random oracle model, and which allows the signing orders to form like any series-parallel graphs. The security is shown by using ID-reduction technique, which reduces the security of multisignature schemes to those of multi-round identification schemes. Furthermore, we discuss the efficiency of the proposed scheme and the upper bound of the possible number of participating signers.

This paper describes fully integrated active guard band filters for suppressing the substrate coupling noise and their noise suppression effect measured by test chip experiments. The noise cancellation circuit of the active guard band filters simply consists of an inverter and a source follower. The substrate noise suppression effect was measured by using a test chip fabricated in a 0.18 µm CMOS triple-well process for system-on-a-chip. The noise with the filter was less than 5% of that without the filter and the noise suppression effect was observed from 1 MHz to 200 MHz by the statistical measurement of the voltage comparator. The noise suppression effect was also observed for actual digital switching noise produced by digital inverters. Configuration of the active guard band filter was investigated by simulation and it is shown that high and uniform noise suppression effect is achieved by placing the guard bands in the L-shape around the target triple-well area on the p-substrate.

A number of results on the estimation of direction of arrival have been obtained based on the assumption that the signal sources are point sources. Recently, it has been shown that signal source localization can be accomplished more adequately with distributed source models in some real surroundings. In this paper, we consider modeling of three-dimensional distributed signal sources, in which a source location is represented by the center angles and degrees of dispersion. We address estimation of the elevation and azimuth angles of distributed sources based on the proposed distributed source modeling in the three-dimensional space using two linear arrays. Some examples are included to more explicitly show the estimation procedures under the model: numerical results obtained by a MUSIC-based method with two uniform linear arrays are discussed.

This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.

This paper presents a case study of synthesis of the industrial embedded microcontroller HT48100 and analysis of performance, cost and software compatibility for its implementation alternatives, using the hardware/software co-design system for microcontrollers/microprocessors PIPER-II. The synthesis tool accepts as input the instruction set architecture (behavioral) specification, and produces as outputs the pipelined RTL designs with their simulators, and the reordering constraints which guide the compiler backend to optimize the code for the synthesized designs. A compiler backend is provided to optimize the application software according to the reordering constraints. The study shows that the co-design approach was able to help the original design team to analyze the architectural properties, identify inefficient architecture features, and explore possible architectural improvements and their impacts in both hardware and software. Feasible future upgrades for the microcontroller family have been identified by the study.

As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary improvements. Experimental results shows that about 8.3% reduction of power dissipation is achieved in the best case.

2-Factor covering designs, a type of combinatorial designs, have recently received attention since they have industrial applications including software testing. For these applications, even a small reduction on the size of a design is significant, because it directly leads to the reduction of testing cost. In this letter, we report ten new designs that we constructed, which improve on the previously best known results.

This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.

This paper presents a novel system-level design methodology, called quality-driven design, by which application-specific optimization can be achieved; furthermore the entire functionality can be shared to maximize design reuse. As a case of study, this paper focuses on quality-driven design for video applications and introduces an output quality adaptive approach based on variable bitwidth optimization to explore a new design space. MPEG2 video is used as the driver application to illustrate the potential of the presented methodology. Experimental results show the effectiveness of the methodology.

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).

Recursive least absolute(RLA) error algorithm is derived which is basically the sign algorithm (SA) combined with recursive estimation of the inverse covariance matrix of the reference input. The name RLA comes from the absolute error criterion. Analysis of the transient behavior and steady-state performance of the RLA algorithm is fully developed. Results of experiment show that the RLA algorithm considerably improves the convergence rate of the SA while preserving the robustness against impulse noise. Good agreement between the simulation and the theoretically calculated convergence validates the analysis.

A blind equalizer which uses the differential constant modulus algorithm (DCMA) is introduced. An anchored FIR equalizer applied to a first-order autoregressive channel and updated according to the DCMA is shown to converge to the inverse of that channel regardless of the initial tap-weights and the gain along the direct path.