This letter proposes a new asymmetric watermarking scheme. In the proposed scheme, a non-full rank matrix is applied to an embedded watermark to form an asymmetric detection watermark. To detect the embedded watermark, the watermarked signal is transformed through the matrix firstly. Then a correlation test between the detection watermark and the transformed signal is performed. This scheme allows for the public release of all information, except for the embedded watermark. The performance of the scheme is analyzed, and the simulation results demonstrate that the proposed scheme is secure and robust to some common attacks.

An order selection scheme for two-sided oblique projection-based interconnect reduction will be investigated. It will provide a guideline for terminating the conventional nonsymmetric Pade via Lanczos (PVL) iteration process. By exploring the relationship of the system Grammians of the original network and those of the reduced network, it can be shown that the system matrix of the reduced-order system generated by the two-sided oblique projection can also be expressed as those of the original interconnect model with some additive perturbations. The perturbation matrix only involves bi-orthogonal vectors at the previous step of the nonsymmetric Lanczos algorithm. This perturbation matrix will provide the stopping criteria in the order selection scheme and achieve the desired accuracy of the approximate transfer function.

This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The technique utilizes a commercially available logic synthesis tool that has been well established for static CMOS logic design, where an intermediate library is devised for logic synthesis likely as static CMOS, and then a resulting synthesized circuit is translated automatically into ASDDL implementation at the gate-level logic schematic level as well as at the physical-layout level. A design example of an ASDDL 16-bit multiplier synthesized in a 0.18-µm CMOS technology shows an operation delay time of 1.82 nsec, which is a 32% improvement over a static CMOS design with a static logic standard-cell library that is finely tuned for energy-delay products. Design with the 16-bit multiplier led to a design time for an ASDDL based dynamic digital circuit 300 times shorter than that using a fully handcrafted design, and comparable with a static CMOS design.

Asymmetric slope differential CMOS (ASD-CMOS) and asymmetric slope differential dynamic logic (ASDDL) surpass the highest speed that conventional CMOS logic circuits can achieve, resulting from deeply shortened rise time along with relatively prolonged fall time. ASD-CMOS is a static logic and ASDDL is a dynamic logic without per-gate synchronous clock signal, each of which needs two-phase operation as well as differential signaling, however, interleaved precharging hides the prolonged fall time and BDD-based compound logic design mitigates area increase. ASD-CMOS 16-bit multiplier in a 0.18-µm CMOS technology demonstrates 1.78 nsec per an operation, which reaches 34% reduction of the best delay time achieved by a multiplier using a CMOS standard cell library that is conventional yet tuned to the optimum in energy-delay products. ASDDL can be superior to DCVS-DOMINO circuits not only in delay time but also in area and even in power. ASDDL 16-bit multiplier achieves delay and power reduction of 4% and 20%, respectively, compared with DCVS-DOMINO realization. A prototype ASD-CMOS 16-bit multiplier with built-in test circuitry fabricated in a 0.13-µm CMOS technology operates with the delay time of 1.57 nsec at 1.2 V.

This paper presents a color demosaicing method by introducing iterative asymmetric average interpolation. Missing primary colors on a Bayer pattern color filter array (CFA) are estimated by an asymmetric average interpolation where less intensity variation is assumed to be of stronger significance, before sharpness of an initial estimate is further improved by an iterative procedure. The iteration is implemented by an observation process followed by a restoration process. The former is modeled by blurring followed by CFA sampling and the latter is completely as same as the color demosaicing method initially applied. Experimental results have shown a favorable performance in terms of PSNR and visual appearance, in particular, in sharpness recovery.

The shared time division multiplexing (shared-TDD) scheme has been proposed to accommodate asymmetric communications between uplink and downlink. The accommodation of connection-less services in Shared-TDD systems causes a difficulty of TDD boundary control. This paper proposes a TDD boundary control (resource assignment) scheme, which can optimize a position of the TDD boundary based on the ratio of uplink to downlink traffic in code division multiple access (CDMA)/shared-TDD systems with connection-less services. The proposed scheme controls the TDD boundary based on the estimated uplink and downlink traffic. Computer simulations show that the proposed scheme effectively controls the radio resource, and thus improves total system throughput performance.

In recently proposed asymmetric watermarking schemes, the public detection is less robust than the private detection. To resolve this problem, a robust asymmetric watermarking scheme using the multiple detection watermarks for public detection is proposed in this letter. In this scheme, the private watermark used for embedding is constructed by secretly selecting the partial elements of those public watermarks. It provides the same robustness for the public and the private detections, and the robustness is demonstrated in the computer simulations.

A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.

SFLASH was chosen as one of the final selection of the NESSIE project in 2003. It is one of the most efficient digital signature scheme and is suitable for implementation on memory-constrained devices such as smartcards. Side channel attacks (SCA) are a serious threat to memory-constrained devices. If the implementation on them is careless, the secret key may be revealed. In this paper, we experimentally analyze the effectiveness of a side channel attack on SFLASH. There are two different secret keys for SFLASH, namely the proper secret key (s,t) and the random seed Δ used for the hash function SHA-1. Whereas many papers discussed the security of (s,t), little is known about that of Δ. Steinwandt et al. proposed a theoretical DPA for finding Δ by observing the XOR operations. We propose another DPA on Δ using the addition operation modulo 232, and present an experimental result of the DPA. After obtaining the secret key Δ, the underlying problem of SFLASH can be reduced to the C* problem broken by Patarin. From our simulation, about 1408 pairs of messages and signatures are needed to break SFLASH. Consequently, SHA-1 must be carefully implemented in order to resist SCA on SFLASH.

We show that the necessary and sufficient condition for the existence of a balanced bowtie decomposition of the symmetric complete multi-digraph is n 5 and λ(n-1) 0 (mod 6). Decomposition algorithms are also given.

A new scheme for watermarking based on vector quantization (VQ) over a binary symmetric channel is proposed. By optimizing VQ indices with genetic algorithm, simulation results not only demonstrate effective transmission of watermarked image, but also reveal the robustness of the extracted watermark.

This paper studies the propagation and crossing of signals in cellular automata whose cells are updated at random times. The signals considered consist of a core part, surrounded by an insulating sheath that is missing at the side of the core that corresponds to the direction into which the signal moves. We study two types of signals: (1) signals by which the sheath at the left and right sides of the core advance first in a propagation step, followed by the core, and (2) signals by which the core advances first, followed by the sheath at its left and right sides. These types naturally arise in, respectively, Moore neighborhood cellular automata with semi-totalistic rules and von Neumann neighborhood cellular automata with symmetric transition rules. The type of a signal has a profound impact on the way signals cross each other, as we show by the construction of one signal of each type. The results we obtained should be of assistance in constructing asynchronous circuits on asynchronous cellular automata.

We propose a mathematical model to analyze the performance of TD-CDMA/TDD systems in terms of call blocking probability and then find the optimum time-slot switching-point at the smallest call blocking probability considering asymmetrical traffic load distribution for various kinds of service applications.

A shared-TDD scheme has been proposed for accommodation of asymmetric communications between uplink and downlink traffic. The application of shared-TDD scheme to CDMA cellular systems causes inter-link interference because CDMA cellular systems use the same frequency band for all cells. This paper proposes a transmission control scheme for uplink packets to relieve the effect of inter-link interference in CDMA/shared-TDD cellular packet systems. In the proposed scheme, mobile stations select transmission slots based on their location and the status of slot allocations in own and the adjacent cells. Computer simulations show that the proposed scheme relieves the effect of inter-link interference, and thus improves the downlink transmission efficiency.

A simple modeling technique for symmetric inductors is proposed. Using the proposed technique, all model parameters for an equivalent circuit of symmetric inductors are easily calculated from geometric, process and substrate resistance parameters without using electromagnetic (EM) simulators. Comparison of simulated results with measured results verifies the effectiveness of the proposed modeling technique up to 5 GHz with center-tapped or non-center-tapped configurations.

Existing routing protocols for mobile ad hoc networks assume that all nodes have the same transmission range. In other words, the mobile ad hoc network has symmetric links, which means that two neighboring nodes A and B are within the transmission range of one another. However, since nodes consume battery power independently according to their computing and communication load, there exist asymmetric links, which means that node A is within node B's transmission range, but not vice versa. In this paper, two approaches are presented to support routing in the existence of asymmetric links: GAHA (GPS-based Hop-by-hop Acknowledgment) and GAPA (GPS-based Passive Acknowledgment) schemes. Both GAHA and GAPA can be applied to any routing protocols by utilizing GPS (Global Positioning System) location information. Simulation results reveal that both GAHA and GAPA protocols cope well in the presence of asymmetric wireless links and nodes' mobility.

By using electro-optic sampling technique, the electric field distribution on a resonant electrode for optical modulation was measured with a resolution in the micrometer range, while the range of measurement area was a few millimeters. The electric field on the asymmetric resonant electrode is enhanced by series and parallel resonance at the electrode. The resonance frequency was shifted by the presence of the electro-optic crystal, which was placed on the electrode for use in the sampling technique. We also showed that the measured electric field distribution at the edges of the electrode was different from the results numerically obtained by an equivalent circuit model.

Asymmetric networks, which provide asymmetric bandwidth or delay for upstream and downstream transfer, have recently gained much attention since they support popular applications such as the World Wide Web (WWW). HTTP (Hypertext Transfer Protocol) is the basis of most WWW services so, evaluating the performance of HTTP on asymmetric networks is increasingly important, particularly real-world networks. However, the performance of HTTP on the asymmetric networks composed of satellite and terrestrial links has not sufficiently evaluated. This paper proposes new formulas to evaluate the performance of both HTTP1.0 and HTTP1.1 on asymmetric networks. Using these formulas, we calculate the time taken to transfer web data by HTTP1.0/1.1. The calculation results are compared to the results of an existing theoretical formula and experimental results gained from a system that combines a VSAT (Very Small Aperture Terminal) satellite communication system for satellite links (downstream) and the Internet for terrestrial links (upstream). The comparison shows that the proposed formulas yield more accurate results (compared to the measured values) than the existing formula. Furthermore, this paper proposes an evaluation formula for pipelined HTTP1.1, and shows that the values output by the proposed formula agree with those obtained by experiments (on the VSAT system) and simulations.

This paper describes an effective technique for coding QCIF video sequences based on a JPEG2000 codec. In the proposed method, multiple frames are combined into one large picture. The larger picture enables images to be coded more efficiently. Image quality is further improved by combining the frames symmetrically. The video sequence is efficiently coded by adapting the time correlation of the video sequences to spatial correlation. We demonstrated the effectiveness of this method by encoding QCIF video sequences using JPEG2000.

Common-mode (CM) radiation from a cable attached to a conducting enclosure has a typical dipole-type antenna structure, in which an equivalent noise voltage source located at the connector excites the attached cable against the enclosure to produce radiated emissions. Based on this mechanism, a simple method for predicting the CM radiation from the cable/enclosure structure was proposed. The method combines an equivalent dipole approximation with sinusoidal current distribution and CM current measurement at a specified location on the cable. Its validity was examined in comparison with the far-field measurement and finite-difference time-domain (FDTD) modeling. The predicted resonance frequencies and CM radiation levels were validated with engineering accuracy, i.e., within 30 MHz and 6 dB, respectively, from the measured and FDTD-modeled results in the frequencies above 150 MHz.