A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(log2n+1)+3log2m) Read/Write operations for a 2nm-bit memory, where n and m are the address width and data width, respectively. Also, the algorithms can verify 100% of the inter-port and intra-port signal misplaced faults of the address, data input, and data output ports.

This paper describes a technique for background digital multistage calibration in the removal of nonlinearities caused by design limitations in pipelined analog-to-digital converters (ADCs). Foreground initialization reduces the calibration time. Furthermore, an improved background skip-and-fill method enables the ADC to trace environmental changes. This method uses a least mean square adaptive algorithm that is digitally implemented with a significantly reduced number of tap coefficients.

We describe a simulation method and design for a stand-alone hybrid power supply system composed of a wind turbine generator and photovoltaic modules. The system has been developed to supply power for telecommunications equipment in areas with no commercial power sources. We also report a comparison of the simulation results with actual measured data. The results show that the hybrid system can function effectively as a power supply for telecommunications equipment.

Public telephone network have been dramatically changing to IP (Internet Protocol) based network. This paper starts with an overview of the present status of the telecommunications network and the rapid evolution of iDCs (internet Data Centers) now underway. Next, we focus on the existing configurations and the characteristics of power systems for IP equipment and iDCs, and then clarify the cutting-edge technologies for highly reliable powering systems and the advantages of DC power systems. Finally, the paper demonstrates energy-saving activities, and the prospected issues to be solved in the field of power systems for the coming full-fledged IT Age.

This paper presents the definition and implementation design of a low power data bus encoding scheme dedicated to system on chip video architectures. Trends in CMOS technologies focus the attention on the energy consumption issue related to on-chip global communication; this is especially true for data dominated applications such as video processing. Taking into account scaling effects a novel coupling-aware bus power model is used to investigate the statistical properties of video data collected in the system bus of a reference hardware/software H.263/MPEG-4 video coder architecture. The results of this analysis and the low complexity requirements drive the definition of a bus encoding scheme called CDSPBI (Coupling Driven Separated Partial Bus Invert), optimized ad-hoc for video data. A VLSI implementation of the coding circuits completes the work with an area/delay/power characterization that shows the effectiveness of the proposed scheme in terms of global power saving for a small circuit area overhead.

This paper considers a motion planning method for humanoid robots. First, we review a modular state net which is a state net representing behavior of a part of the humanoid robots. Each whole body motion of the humanoid robots is represented by a combination of modular state nets for those parts. In order to obtain a feasible path of the whole body, a timed Petri net is used as an abstracted model of a set of all modular state nets. Next, we show an algorithm for constructing nonlinear dynamics which describes a periodic motion. Finally, we extend the state net in order to represent primitive periodic motions and their transition relation so that we can generate a sequence of primitive periodic motions satisfying a specified task.

A batch process is a typical concurrent system in which multiple interacting tasks are carried out in parallel on several batches at the same time. A major difficulty in designing a batch control system is the lack of modeling techniques. This paper aims at developing a method of constructing batch control system models in a hierarchical manner and operating batch processes using the constructed models. For this purpose, it first defines process and plant specifications described by partial languages, next presents a procedure for constructing hierarchical Petri net based models, and states the verification of models based on reachability analysis. It also discusses the detection of faults and conflicts in batch processes based on place-invariant analysis.

A double surface light emission backlight that uses single light-guide plate, has been developed for illumination of two liquid-crystal displays (LCD) on its front and rear, to be used in a cellular phone. The light-guide plate has a trapezoid cross-section with arrays of optical micro deflector and micro prism on the front and the rear surfaces, respectively. Propagated light, forward and backward, inside the light-guide plate are controlled and directed toward LCDs using only two prism sheets with internal reflection characteristic, each for the front and the rear. Only three optical components and four light-emitting diodes (LEDs) are used in the new structure compared with ten components and six LEDs of the current type. Comparing with the current type, the thickness and power consumption of the new backlight are reduced by a factor of 0.59 and 0.67, respectively.

We propose a multiple-subcarrier (MS) optical communication system using intensity modulation with direct detection (IM/DD) with peak reduction carriers (PRCs) to improve the power efficiency of IM/DD MS systems. The proposed system transmits L subcarriers referred to as PRCs among N subcarriers for the d.c. bias reduction so that the optical power is reduced. Since information bits are mapped onto each subcarrier other than PRCs independently, the information bits of each subcarrier can be detected independently and the error rate of the proposed system is unaffected by PRCs.

We study analysis of hybrid systems under incomplete knowledge. The class of hybrid systems to be considered is assumed to have the form of a rectangular hybrid automaton such that each constant in invariants and guards is given as a parameter. We develop a method based on symbolic computation that computes an approximation of the discrete behavior of the automaton. We also show an implementation on a constraint logic programming language.

To fulfill the computing demands in visual media processing, we have been investigating a parallel processing system to improve the processing speed of the visual media related to applications from the point of view of a memory system within a single instruction multiple data (SIMD) computer. In this paper, we have introduced MAMS-PP4, which is similar to a pipelined SIMD architecture type and consists of pq processing elements (PEs) as well as a multi-access memory system (MAMS). MAMS supports simultaneous access to pq data elements within a horizontal (1 pq), a vertical (pq 1) or a block (p q) subarray with a constant interval in an arbitrary position in an M N array of data elements, where the number of memory modules, m, is a prime number greater than pq. MAMS reduces the memory access time for an SIMD computer and also improves the cost and complexity that involved in controlling the large volume of data demanded in visual media applications. PE is designed to be a two-state machine in order to utilize MAMS efficiently. MAMS-PP4 was fabricated into ASIC using TOSHIBA TC240C series library and a test board was used to measure the performance of ASIC. The test board consists of devices such as an MPC860 embedded-PCI board, two ASICs and a FPGA for the control units. Experiment was done on various computer systems in order to compare the performance of MAMS-PP4 using morphological operations as the application. MAMS-PP4 shows a respectful and consistent processing speed.

This paper addresses the scheduling problem of a class of automated manufacturing systems with multiple resource requests. In the automated manufacturing system model, a set of jobs is to be processed and each job requires a sequence of operations. Each operation may need more than one resource type and multiple identical units with the same resource type. Upon the completion of an operation, resources needed in the next operation of the same job cannot be released and the remaining resources cannot be released until the start of the next operation. The scheduling problem is formulated by Timed Petri nets model under which the scheduling goal consists in sequencing the transition firing sequence in order to avoid the deadlock situation and to minimize the makespan. In the proposed genetic algorithm with deadlock-free constraint, Petri net transition sequence is coded and a deadlock detection method based on D-siphon technology is proposed to reschedule the sequence of transitions. The enabled transitions should be fired as early as possible and thus the quality of solutions can be improved. In the fitness computation procedure, a penalty item for the infeasible solution is involved to prevent the search process from converging to the infeasible solution. The method proposed in this paper can get a feasible scheduling strategy as well as enable the system to achieve good performance. Numerical results presented in the paper show the efficiency of the proposed algorithm.

Nonminimum phase systems are difficult to be controlled with a conventional PID-type controller because of their inherent characteristics of undershooting. A neuro-controller combined with a PID-type controller has been shown to improve the control performance of the nonminimum phase systems while maintaining stability. In this paper, we apply a multiobjective evolutionary optimization method for training the neuro-controller to reduce the undershooting of the nonminimum phase system. The computer simulation shows that the proposed multiobjective approach is very effective and suitable because it can minimize the control error as well as reduce undershooting and chattering. This method can be applied to many industrial nonminimum phase problems with ease.

We develop an algorithm for a controller design method for Max-Plus Linear (MPL) systems with selective parameters. Since the conventional algorithm we proposed requires high computational load when the prediction horizon is large, two methods for reducing the calculation time are proposed. One is based upon the branch-and-bound method, and the other is to reuse the optimal solution. The effectiveness of these two methods is confirmed through numerical simulation.

Electronic Toll Collection (ETC), an application of Dedicated Short Range Wireless Communication (DSRC), had suffered from wrong operations due to multipath problems. To solve this problem, we proposed to apply a simple configured path determination scheme for the ETC system. The system consists of a vector network analyzer, low-noise amplifier, and X-Y positioner and achieves an automatic measurement of the spatial transfer function with emphasis on accurate measurement and reproducibility. For the reliable identification of the propagating paths, 3-D Unitary ESPRIT and SAGE algorithms were employed. Having developed the system, field experiments at the toll gate of the highway was carried out. In the measurements, we could determine many propagation paths so that the dominant propagation phenomena at the toll gate was identified. They included a ground-canopy twice reflected wave, which was a potential path that caused wrong operation. Consequently, their reflection coefficients and polarization characteristics were investigated. From the results, applicability of the path determination system for short range on-site measurement was confirmed.

Energy consumption is one of the most critical constraints in the design of portable embedded systems. This paper describes an empirical study about the impacts of compiler optimizations on the energy consumption of the address bus between processor and instruction memory. Experiments using a number of real-world applications are presented, and the results show that transitions on the instruction address bus can be significantly reduced (by 85% on the average) by the compiler optimizations together with bus encoding.

A workflow definition containing errors might cause serious problems for an enterprise especially when it involves mission critical business processes or inter-organizational interaction. So workflow definitions should be defined in a strict and rigorous way. In this paper, we develop a workflow definition language and analysis methods for the language to support strict and rigorous workflow definitions. Faults or mistakes causing communication deadlock, access conflicts, and improper exception specification in workflow definitions can be detected and notified automatically using the methods. The proposed workflow definition language borrows structured constructs of conventional programming languages because many good features of conventional programming languages also can be used effectively in expressing workflow processes. With slight modifications and scope restrictions, the developed analysis techniques in this paper can be used in any workflow definition languages and they can help workflow designers define workflow processes in much more safe and reliable manner.

This paper proposes a new SSB-QPSK modulation/demodulation method. The present method multiplexes the USB (Upper Side Band) and LSB (Lower Side Band) of a QPSK-modulated SSB (Single Side Band) on the same SSB complex frequency band. The present method thus achieves 2 bit/s/Hz. This method is an orthogonal SSB-QPSK method, because the multiplex signals are orthogonal to each other. The demodulator consists of two SSB demodulators. A simulation result in AWGN conditions, shows that the proposed method has better BER (Bit Error Rate) performance than 16 QAM. The degradation of BER in comparison with QPSK is less than 0.2 dB on Eb/No (bit-energy-to-noise-power ratio). In a fading/Doppler environment, the BER performance of the orthogonal SSB-QPSK is the same as that of QPSK.

This letter considers relationship between cyclic digital-to-analog converters (DACs) and iterated function systems (IFSs). We introduce the cyclic DACs as inverse systems of analog-to-digital converters in terms of one-dimensional maps. We then compare the DACs with a typical example of existing applications of IFSs: chaos game representation for analysis of DNA structures. We also present a simple test circuit of a DAC for Gray decoding based on switched capacitors and confirm the basic operation experimentally.

This letter presents a new probability expression for a multi-carrier (MC) DS/CDMA acquisition system with a reference matched filter (RMF). To evaluate the mean acquisition time (MAT) as a measure of the system performance, the probabilities of detection, miss, and false alarm are derived. From the results, it is shown that the MAT of the MC-CDMA hybrid system with RMF is comparable to the optimum mean acquisition time of the conventional MC-CDMA hybrid system, maintaining approximately the same degree of structuring complexity.