In this paper, we evaluate the throughput performance of CDMA Slotted ALOHA systems. To improve the throughput performance, we employ the Quasi-synchronous sequences and the Modified Channel Load Sensing Protocol as an access control procedure. As a result, we found a good throughput by the QS-sequences. By employing MCLSP, we can keep the maximum throughput even in high offered load and in the presence of a long access timing delay, which is one of the issue in satellite packet communication systems.

The one of the problems in the satellite packet communication system is the existence of a long time delay, which may cause an improper packet access control resulting in a great deal of degradation of the system performance. In this paper, we clarify the effect of long time delay on the performance of CDMA ALOHA systems and then propose a new access control protocol, called Modified Channel Load Sensing Protocol (MCLSP), for the CDMA ALOHA systems. As a result, we show that a significant improvement in the throughput performance was obtained with MCLSP even in the presence of a long time delay.

This paper presents a new timing-driven global routing method for standard cell layout. The proposed method can explicitly consider the timing constraint between two registers and minimize the channel density under the given timing constraint. In the proposed method, first, we determine the initial global routes. Next, we improve the global routes to satisfy the timing constraint between two registers as well as to minimize the channel density. Finally, for each cell row, the nets incident to terminals on the cell row are assigned to channels to minimize the channel density using 0-1 integer linear programming. We also show the experimental results of the proposed method implemented on an engineering workstation. Experimental results show that the proposed method is quite promising.

Throughput analysis of CDMA Unslotted ALOHA with channel load sensing protocol (CLSP) is presented in consideration of the effect of the access timing delay. The access timing delay is defined as the sum of the process time and the propagation time for the packet access control. As CLSP is the scheme to control packet generation by the channel state information from the hub station, the effect of the access timing delay is significant. In our analysis, we extend a continuous-time Markov chain model and queueing systems. As a result, we found degradations of the throughput performance due to the access timing delay. For the value of CLSP threshold, we show that it is smaller than the case without the access timing delay in order to achieve satisfactory throughput. Furthermore, for a large access timing delay, CLSP makes no sense and the throughput is worse than the system without employing CLSP.

Orthogonal frequency division multiplexing (OFDM) has been receiving a lot of attention in the field of broadcasting because of its ruggedness under multipath environments. One of important issues to realize high quality reception of OFDM signals is to correct frequency and timing offsets between the transmitter and receiver so that orthogonality of the carriers can be maintained. This paper discusses a frequency and timing period acquisition technique for OFDM systems. A new offset estimation technique is introduced that detects both the frequency and timing peirod offsets at the same time by using only one pilot symbol with its suitable frequency assignment. A pseudo noise (PN) sequence is also introduced to assign these frequencies of the pilot symbol so that the frequency acquisition range can be widened. Numerical examples are given to show the estimate variances of the proposed frequency and timing period estimator over both additive white Gaussian noise (AWGN) and multipath fading channels. Also the bit error rate (BER) performance for an open loop acquisition system is examined.

This paper proposes a fast timing recovery method with a decision feedback equalizer for baudrate sampling. The proposed method features two special techniques. The first one is for coarse estimation of the sampling phase. Internal signals of the oversampled analog-to-digital converter at different phases are directly taken out for parallel evaluation. The second technique provides fine tuning with a phase-modification stepsize which is adaptively controlled by the residual intersymbol interference. Simulation results by a full-duplex digital transmission system with a multilevel line code show superiority of the proposed method. The coarse timing estimation and the fine tuning reduce 75% and 40% of the time required by the conventional method,respectively. The overall saving in timing recovery is almost 60% over the conventional method. The proposed method could easily be extended to other applications with a decision feedback equalizer.

We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.

Retiming is a technique to resynthesize a synchronous sequential circuit by rearranging flip-flops. In view of logic optimization, retiming can potentially derive a circuit which is more simplified and testable because retiming can convert several sequential redundancies into combinational redundancies. Retiming methods proposed before have no guarantee to generate the same output sequences when the circuit start from a specified initial state such as the reset state. If the circuit with a specified initial state must have the same output sequences after retiming, rearrangement of flip-flops should be restricted. This paper presents a retiming method for circuits with a specified initial state so that retimed circuits give the same output sequences of the original circuits for any input sequences. In the proposed method, during the procedure of retiming each flip-flop keeps a value corresponding to the initial state and unification of flip-flops with different value is avoided. Our procedures uses 5-valued logic on gate level implementation to describe and calculate the values of flip-flops. Therefore after optimization using our method, the circuit has completely the same behavior as that of the original. Experimental results for ISCAS'89 benchmark circuits show the method can be used to optimize the circuits as well as a method without considering the initial state. And testability of the retimed circuit is more enhanced than that of the original circuit.

This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.

The performance of coded multi-pulse pulse position modulation (MPPM) consisting of m slots and 2 pulses, denoted as (m, 2) MPPM, with imperfect slot synchronization is analyzed. Convolutional codes and Reed-Solomon (RS) codes are employed for (m, 2) MPPM, and the bit error probability of coded (m, 2) MPPM in the presence of the timing offset is derived. In each coded (m, 2) MPPM, we compare the performance of some different code rate systems. Moreover, we compare the performance of both systems at the same information bit rate. It is shown that in both coded systems, the performance of code rate-1/2 coded (m, 2) MPPM is the best when the timing offset is small. Wheji the timing offset is somewhat large, however, uncoded (m, 2) MPPM is shown to perform better than coded (m, 2) MPPM. Further, convolutional coded (m, 2) MPPM with the constraint length k7 is shown to perform better than RS coded (m, 2) MPPM for the same code rate.

We are developing multimodal man-machine interfaces through which users can communicate by integrating speech, gaze, facial expressions, and gestures such as nodding and finger pointing. Such multimodal interfaces are expected to provide more flexible, natural and productive communications between humans and computers. To achieve this goal, we have taken the approach of modeling human behavior in the context of ordinary face-to-face conversations. As the first step, we have implemented a system which utilizes video and audio recording equipment to capture verbal and nonverbal information in interpersonal communications. Using this system, we have collected data from a task-oriented conversation between a guest (subject) and a receptionist at company reception desk, and quantitatively analyzed this data with respect to multi-modalities which would be functional in fluid interactions. This paper presents detailed analyses of the data collected: (1) head nodding and eye-contact are related to the beginning and end of speaking turns, acting to supplement speech information; (2) listener responses occur after an average of 0.35 sec. from the receptionist's utterance of a keyword, and turn-taking for tag-questions occurs after an average of 0.44 sec.; and (3) there is a rhythmical coordination between speakers and listeners.

This paper reviews very high-speed optical signal processing technology based on the instantaneous characteristic of optical nonlinearities. Focus is placed on 100-Gbit/s optical time-division multiplexing (TDM) transmission systems. The key technologies including ultrashort optical pulse generation, all-optical multiplexing/demultiplexing and optical timing extraction techniques are alse described together with their major issues and future prospects.

This paper discusses an all-optical tank circuit that uses the comb-shaped gain spectrum generated by a Brillouin amplifier. The theory of timing clock extraction is shown for two cases: with two gains and with three gains. In both cases, the waveform of the extracted timing clock is simulated. According to the simulation, unlike an ordinary tank circuit, the amplitude of the extracted clock is not constant even though the quality factor (Q) is infinite. The extracted clock is clearly influenced by the pattern of the original data stream if the Brillouin gain is finite. The ratio of the maximum extracted clock amplitude to the minimum extracted amplitude is calculated as a function of Brillouin gain. The detuning of the pump light frequency is also discussed. It induces not only changes in the Brillouin gain, but also phase shift in the amplified light. The relation between the frequency drift of the pump lights and the jitter of the extracted timing clock is shown, in both cases: two pump lights are used and three pump lights are used. It is numerically shown that when the all pump lights have the same frequency drift, i.e., their frequency separation is constant, the phase of the extracted clock is not influenced by the frequency drift of the pump lights. The operation principle is demonstrated at 5Gbit/s, 2.5Gbit/s, and 2Gbit/s using two pumping techniques. The parameters of quality factor and the suppression ratio in the baseband domain are measured. Q and the suppression ratio are found to be 160 and 28dB, respectively.

This paper presents a new LP based optimal cell selection method. Optimal cell selection is useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle cycle time optimization. We also make a useful initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it can speed up a 13k-transistor circuit of a manual chip design by 17% without any increase of area.

This paper presents a fully digital high speed (60 Mb/s) Quadrature Phase Shift Keying (QPSK)/Offset QPSK (OQPSK) burst demodulator for radio applications, which has been implemented on a 0.5 µm Complementary Metal Oxide Semiconductor (CMOS) master slice Very Large Scale Integrated circuit (VLSI). The developed demodulator VLSI eliminates analog devices such as mixers, phase-shifters and Voltage Controlled Oscillator (VCO) for bit-timing recovery, which are used by conventional high-speed burst demodulators. In addition to the fully digital implementation, the VLSI achieves fast carrier and bit-timing acquisition in burst modes by employing a reverse-modulation carrier recovery scheme with a wave-forming filter for OQPSK operation, and a bit-timing recovery scheme with bit-timing estimation and interpolation using a pulse-shaping filter. Results of performance evaluation assuming application in Time Division Multiple Access (TDMA) systems show that the developed VLSI achieves excellent bit-error-rate and carrier-slipping-rate performance at high speed (60 Mb/s) with short preamble words (less than 100 symbols) in low Eb/No environments.

A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.

The performance of multi-pulse pulse position modulation (MPPM) consisting of m slots and 2 pulses, denoted as (m, 2) MPPM, with imperfect slot synchronization is analyzed. The word error probability of (m, 2) MPPM in the presence of timing offset is analyzed, and the optimum symbol sets of (m, 2) MPPM minimizing the symbol error probability are assigned. When an unassigned symbol is detected, the receiver decodes the unassigned symbol as one of the assigned symbols having the highest probability of transition from the assigned symbol to the unassigned symbol. The bit error probability of (m, 2) MPPM in the presence of the timing offset is analyzed, and the bit error probability of (m, 2) MPPM is compared with that of PPM for the same transmission bandwidth and the same transmission rate. Moreover, the bit error probability of (m, 2) MPPM synchronized by a phase-locked loop (PLL) is also analyzed. It is shown that a word with two continuous pulses has better performance than a word with two separate pulses. It is also shown that when the timing offset occurs, and when the slot clock is synchronized by a PLL, (m, 2) MPPM performs better than PPM because (m, 2) MPPM has the optimum assigned symbols, and can decode detected words more correctly than PPM.

In order to investigate the jitter characteristics of PLLs for practical applications, we have developed a computer simulation program of PLL, which can deal with arbitrary patterns both of data and jitters, as well as a conceivable nonlinearity of the circuit performance. We used a time-domain method, namely, we solved the state equation of a charge pump type PLL with a constant time step. The jitter transfer characteristics of a conventional PLL were calculated for periodic input data patterns with sinusoidal jitters. The result agreed fairly well with the corresponding experiments. And we have revealed that an ordinary PD (Phase Detector), which detects the phase difference between input and VCO signals at only rising edges, shows the folded jitter transfer characteristics at the half of the equivalent frequency of the input signal. This folded jitter characteristics increases the total jitter for long successive '1' or '0' data patterns, because of their low equivalent sampling frequency, and might increase the jitter even for the random data patterns. Based on simulation results, we devised an improved phase detector for PLL having a low jitter characteristics. And we also applied the simulation to an FDD (Frequency Difference Detector) type fast pull-in PLL which we have proposed recently, and obtained that the jitter of it was smaller than that of a conventional PLL by 25% for PRBS (pseudo random bit sequence) NRZ code.

Recent progress on the ultrahigh-speed optical transmission experiments are reviewed including the ultrashort pulse generation, high-speed timing extraction, all-optical multi/demultiplexing. Also discussed are the latest 100 Gbit/s experiments and a scope to higher bit-rate, longer distance optical transmission.

The timing jitter reductions with differently shaped optical bandpass filters are discussed and the transmission distance achievable against the timing jitter is evaluated using optical bandpass filters in several tens of Gb/s soliton transmission. Experimental confirmation of timing jitter reduction with optical bandpass filters is demonstrated in 10Gb/s optical soliton recirculating loop experiments by measuring the timing jitter and the bit error rates.