We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116 MHz clock rate. A speedup of far more than10 is achieved compared to conventional methods including GPU implementation.

We propose an optimization method for power distribution network that explicitly deals with timing. We have found and focused on the facts that decoupling capacitance (decap) does not necessarily improve gate delay depending on the switching timing within a cycle and that power wire expansion may locally degrade the voltage. To resolve the above facts, we devised an efficient sensitivity calculation of timing to decap size and power wire width for guiding optimization. The proposed method, which is based on statistical noise modeling and timing analysis, accelerates sensitivity calculation with an approximation and adjoint sensitivity analysis. Experimental results show that decap allocation based on the sensitivity analysis efficiently minimizes the worst-case circuit delay within a given decap budget. Compared to the maximum decap placement, the delay improvement due to decap increases by 3.13% even while the total amount of decaps is reduced to 40%. The wire sizing with the proposed method also efficiently reduces required wire resource necessary to attain the same circuit delay by 11.5%.

An accurate and rapid synchronization scheme is a prerequisite for achieving high-quality multimedia transmission for wireless handheld terminals, e.g. China multimedia mobile broadcasting (CMMB) system. In this paper, an efficient orthogonal frequency division multiplexing (OFDM) timing synchronization scheme, which is robust to the doubly selective fading channel, is proposed for CMMB system. TS timing is derived by performing an inverse sliding correlation (ISC) between the segmented Sync sequences in the Beacon, which possesses the inverse conjugate symmetry (ICS) characteristic. The ISC can provide sufficient correlative gain even in the ultra low signal noise ratio (SNR) scenarios. Moreover, a fast fine symbol timing method based on the auto-correlation property of Sync sequence is also presented. According to the detection strategy for the significant channel taps, the specific information about channel profile can be obtained. The advantages of the proposed timing scheme over the traditional ones have been demonstrated through both theoretical analysis and numerical simulations.

Post-silicon tuning is attracting a lot of attention for coping with increasing process variation. However, its tuning cost via testing is still a crucial problem. In this paper, we propose tuning-friendly body bias clustering with multiple bias voltages. The proposed method provides a small set of compensation levels so that the speed and leakage current vary monotonically according to the level. Thanks to this monotonic leveling and limitation of the number of levels, the test-cost of post-silicon tuning is significantly reduced. During the body bias clustering, the proposed method explicitly estimates and minimizes the average leakage after the post-silicon tuning. Experimental results demonstrate that the proposed method reduces the average leakage by 25.3 to 51.9% compared to non clustering case. In a test case of four clusters, the number of necessary tests is reduced by 83% compared to the conventional exhaustive test approach. We reveal that two bias voltages are sufficient when only a small number of compensation levels are allowed for test-cost reduction. We also give an implication on how to synthesize a circuit to which post-silicon tuning will be applied.

Dual-vdd has been proposed to optimize the power of circuits without violating the performance. In this paper, different from traditional methods which focus on making full use of slacks of non-critical gates, an efficient min-cut based voltage assignment algorithm concentrating on critical gates is proposed. And then this algorithm is integrated into a searching engine to auto-select rational voltages for dual-vdd system. Experimental results show that our search engine can always achieve good pair of dual-vdd, and our min-cut based algorithm outperformed previous works for voltage assignment both on power consumption and runtime.

This paper proposes a third-order low-distortion delta-sigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a non-overlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4-bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.

In this letter, a timing-offset estimation scheme is proposed for cooperative networks. The estimation scheme consists of coarse timing-offset estimation and fine timing-offset estimation. The presented scheme relies on periodic training data and linear mean square estimation for efficient estimation. The simulation results indicate that the performance of the proposed approach is better than or comparable to that of the conventional methods with lower computational complexity in the fine estimation.

In this letter, an improved residual symbol timing offset (STO) estimation scheme is suggested in an orthogonal frequency division multiplexing (OFDM) based digital radio mondiale plus (DRM+) system with cyclic delay diversity (CDD). The robust residual STO estimator is derived by properly selecting the amount of cyclic delay and a pilot pattern in the presence of frequency selectivity. Via computer simulation, it is shown that the proposed STO estimation scheme is robust to the frequency selectivity of the channel, with a performance better than the conventional scheme.

This letter proposes two efficient schemes for the joint estimation of symbol timing offset (STO) and carrier frequency offset (CFO) in orthogonal frequency division multiplexing (OFDM) based IEEE 802.16e systems. Avoiding the effects of inter symbol interference (ISI) over delay spread by the multipath fading channel is a primary purpose in the letter. To do this, the ISI-corrupted CP is excluded when a correlation function is devised for both schemes, achieving the improved performance. To demonstrate the efficiency of the proposed methods, the performance is compared with the conventional method and is evaluated by the mean square error (MSE), acquisition range of CFO, and complexity comparison.

In this letter, we propose and analyze a cooperative transmission scheme (CTS) that uses transmission timing control for LTE enterprise femtocells. In our scheme, the user equipment (UE) can receive the desired signal from an adjacent fBS as well as its serving femtocell BS (fBS). Thus, UE achieves an improved signal to interference ratio (SIR) due to the synchronization of the two signals. Analysis and simulation results show that the proposed scheme can reduce the outage probability for enterprise femtocells compared to the conventional system. In particular, a significant performance improvement can be achieved for UEs located at cell edges.

PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error.

In this letter, we present a novel timing offset estimation method for chirp-based communication systems which is robust against frequency offset. For robust timing offset estimation, we propose a partial cross-correlation and differential multiplication method using up and down chirp symbols. The performances of the proposed estimator in indoor multipath channel model provided by IEEE 802.15.4a standard are presented in terms of mean-square error (MSE) obtained by computer simulation. The simulation results show that the proposed estimator has a significantly smaller MSE than the conventional estimators.

The statistical static timing analysis has been studied intensively in the last decade so as to deal with the process variability, and various techniques to represent distributions of timing information, such as a gate delay, a signal arrival time, and a slack, have been proposed. Among them, the Gaussian mixture model is distinguished from the others in that it can handle various correlations, non-Gaussian distributions, and slew distributions easily. However, the previous algorithm of computing the statistical maximum for Gaussian mixture models, which is one of key operations in the statistical static timing analysis, has a defect such that it produces a distribution similar to Gaussian in a certain case, although the correct distribution is far from Gaussian. In this paper, we propose a new algorithm for statistical maximum (minimum) operation for Gaussian mixture models. It takes the cumulative distribution function curve into consideration so as to compute accurate criticalities (probabilities of timing violation), which is important for detecting delay faults and circuit optimization with the use of statistical approaches. We also show some experimental results to evaluate the performance of the proposed method.

This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.

A zig-zag Gardner algorithm with parallel architecture is presented in this letter. This algorithm performs timing adjustment in each individual burst independently for high speed wireless burst communication with a short guard. Over sampling data are stored in RAM initially and read forward and backward alternately later. The proposed algorithm has distinct symmetric characteristic in the forward and backward process, which makes the alternate sequences achieve nearly the same effect as a continuous sequence. The performance of the proposed algorithm is very close to the theoretical curve.

Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

Frequency-domain equalization (FDE) based on minimum mean square error (MMSE) is considered as a promising equalization technique for a broadband single-carrier (SC) transmission. When a square-root Nyquist filter is used at a transmitter and receiver to limit the signal bandwidth, the presence of timing offset produces the inter-symbol interference (ISI) and degrades the bit error rate (BER) performance using MMSE-FDE. In this paper, we discuss the mechanism of the BER performance degradation in the presence of timing offset. Then, we propose joint MMSE-FDE & spectrum combining which can make use the excess bandwidth introduced by transmit filter to achieve larger frequency diversity gain while suppressing the negative effect of the timing offset.

Hop-timing detection is of extreme importance for the reception of frequency hopping (FH) signals. Any error in the hop-timing detection has a deleterious effect on the performance of the receiver in frequency hopping (FH) communication systems. However, it is not easy to detect the hop-timing under low signal to noise power ratio (SNR) environments. Adaptive array antennas (AAA) have been expected to improve the performance of FH communication systems by beamforming for the direction of arrival of the desired signal. Since the conventional AAA exploits at least the coarse synchronization for dehopping of FH signals before achieving the beamforming, any fault in the hop-timing detection causes the deterioration of the performance of AAA. Using AAA based on the constant modulus algorithm (CMA), this paper proposes a new method for blind beamforming and hop-timing detection for FH signals. The proposed method exploits both the spatial and temporal characteristics of the received signal to accomplish the beamforming and detect the hop-timing without knowing any a priori information such as fine/coarse time synchronization and training signal. The performance verifications of the proposed method based on pertinent simulations are presented.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.

This paper proposes a modified per-survivor iterative timing recovery scheme, which exploits a new split-preamble strategy in conjunction with a per-survivor processing soft-output Viterbi algorithm (PSP-SOVA). The conventional split-preamble strategy places a preamble at the beginning of a data sector and uses it to run a phase-locked loop during acquisition to find an initial phase/frequency offset. However, the proposed scheme splits the preamble into two parts. The first part is placed at the beginning of the data sector, whereas the second part is divided into small clusters, each of which is then embedded uniformly within the data stream. This split preamble is utilized to adjust the branch metric calculation in PSP-SOVA to ensure that the survivor path occurs in a correct direction. Results indicate that the proposed scheme yields a better performance than a conventional receiver with separate timing recovery and turbo equalization, and the iterative timing recovery scheme proposed in [1],[2], especially when the timing jitter is large. In addition, we also show that the proposed scheme can automatically correct a cycle slip much more efficiently than the others.