In this letter, a concept of virtual smart antenna (SA) is introduced for OFDM-based cellular systems with a frequency reuse factor equal to 1. A method of estimating intercell symbol timing offsets (STOs) from received OFDM signals impinging on virtual antenna is proposed for users at a cell boundary. Also, adaptive beamforming methods for virtual SA are proposed to reduce intercell interference (ICI) from adjacent base stations (BSs).

This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure are obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.

A robust joint symbol timing and fractional frequency offset estimator for OFDM systems in multipath fading channels is proposed based on cyclic shifting and autocorrelation properties of PN codes. A new timing metric is also introduced by considering the delay spread to improve the robustness of the estimator in the multipath fading channels.

Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted.

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

A timing-driven placement algorithm based on path topology analysis is presented. The optimization for path delay is transformed into cell location optimization. The algorithm pays much attention on path topologies and applies an effective force directed method to find cell target locations. Total wire length optimization is combined with the timing-driven placement algorithm. MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks are experimented and results show that our timing-driven placement algorithm can make the longest path delay improve up to 13% compared with wirelength driven placement.

This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits. Experimenting with the STARI and DME circuits, the proposed approach shows its effectiveness.

As the complexity of VLSI circuits increases, the routability problem becomes more and more important in modern VLSI design. In general, the flexibility improvement of the edges in a routing tree has been exploited to release the routing congestion and increase the routability in the routing stage. Given an initial rectilinear Steiner tree, the rectilinear Steiner tree can be transformed into a Steiner routing tree by deleting all the corner points in the rectilinear Steiner tree. Based on the definition of the routing flexibility in a Steiner routing tree and the timing-constrained location flexibility of the Steiner-point in any Y-type wire, the simulated-annealing-based approach is proposed to construct a better timing-constrained flexibility-driven Steiner routing tree by reassigning the feasible locations of the Steiner points in all the Y-type wires. The experimental results show that our proposed algorithm, STFSRT, can increase about 0.005-0.020% wire length to improve about 43-173% routing flexibility for the tested benchmark circuits.

A robust time and frequency synchronization scheme is proposed for the high rate OFDM-based wireless local area networks (WLANs). The IEEE 802.11a standardized preamble is efficiently utilized and makes the proposed scheme practical. Simulation results under different channel environments are presented to illustrate the effectiveness of the proposed scheme.

This paper proposes a simple timing synchronization method in order to design a timing synchronization circuit with low-complex and low-volume digital signal processing (DSP) for orthogonal frequency division multiplexing (OFDM) packet transmission systems. The proposed method utilizes the subtraction process for acquirement of a timing metric of fast Fourier transform (FFT) window, whereas the conventional methods utilize the multiplication process. This paper adopts the proposed method to a standardized OFDM format, IEEE 802.11a, and elucidates that the proposed one shows good transmission performance as well as the conventional one in fast time-variant multi-path Rayleigh fading channels by computer simulation.

Spatial correlation among antenna elements both at transmitter and receiver sides in MIMO communications is known to have a crucial impact on system performances. Another factor that can severely degrade receiver performances is the timing offset relative to the channel delay profile. In this paper we derive a novel receiver for turbo MIMO equalization in space-time-trellis-coded (STTrC) system to jointly address the problems described above. The equalizer is based on low complexity MMSE filtering. A joint detection technique of the several transmit antennas is used to reduce the receiver's sensitivity to the spatial correlation at the transmitter and receiver sides. Furthermore, only the significant portion of the channel impulse response (CIR) is taken into account while detecting signals. The remaining portion of CIR is regarded as the unknown interference which is effectively suppressed by estimating its covariance matrix. By doing this the receiver's complexity can be reduced since only a portion of the CIR has to be estimated and used for signal detection. Furthermore, by suppressing the interference from the other paths outside the equalizers coverage the receiver's sensitivity to the timing offset can be reduced. The proposed receiver's performance is evaluated using field measurement data obtained through multidimensional channel sounding. It is verified through computer simulations that the performance sensitivity of the joint detection-based receiver to the spatial correlation is significantly lower than with the receiver that detects only one antenna at a time. Furthermore, the performance sensitivity to the timing offset of the proposed receiver is shown to be significantly lower than that of the receiver that ignores the existence of the remaining multipath CIR components.

The bit error rate (BER) degradations of fast frequency hopping multiple access (FFH-MA) systems due to the frequency and timing offsets are investigated over a Rician fading channel. It is shown that as the received average SNR increases, the BER is affected much larger by frequency and timing offsets. When the frequency offset or the timing offset exists alone, the BER of the FFH-MA system is degraded much more due to the timing offset than due to the frequency offset. The BER degradation due to both the frequency offset and the timing offset is larger than the sum of the degradations due to each offset.

The problem of estimating code timings in DS-CDMA systems with multiple antennas is considered in the presence of multipath time-varying fading channels and near-far environments. We present an efficient algorithm for an approximate maximum likelihood approach of jointly estimating the multipath timings of a desired user for DS-CDMA systems that consist of multiple antennas either uncorrelated or fully correlated in space. The procedures of the algorithm to estimate code-timings are developed in order to better exploit the time-varying characteristics of the fading process. In the multipath fading channels, the solution of the proposed algorithms is based on successively optimizing the criterion for increasing numbers of multipath delays. It is shown via simulation results that the modified approaches of the approximate maximum likelihood algorithm much more improve its acquisition performance in the time-varying fading channels. It is seen that the acquisition performance of multiple antennas based acquisition scheme is much better than that of a single antenna based timing estimator in the presence of multipath fading channels and the near-far problem. Furthermore, it is observed that the proposed algorithms outperform the correlator and MUSIC estimator in the multiuser environments with near-far situation on time-varying Rayleigh fading channels.

The uplink synchronous transmission scheme was proposed to improve the uplink performance of DS-CDMA systems. However, previous performance analyses have assumed perfect uplink synchronization among main paths, which is impractical due to timing misalignment. Accordingly, this Letter evaluates the impact of imperfect synchronization on the performance of an uplink synchronized DS-CDMA system by deriving an orthogonality factor as a measure of the imperfection in synchronization.

This letter derives and computes the detection probability for timing synchronization in an orthogonal frequency division multiplexing (OFDM) system encountered with a multipath Rayleigh fading channel. OFDM timing synchronization using constant amplitude zero auto-correlation (CAZAC) training symbols and correlation techniques is adopted. With this provision, we focus on the numerical analysis for OFDM timing synchronization scheme employing a preadvancement technique to reduce the inter-symbol interference (ISI). For measuring system performance, the sync detection performance derived in the considered system is presented in a multipath Rayleigh fading channel.

This paper proposes a time alignment control (TAC) for reducing an influence of multiple access interference (MAI) due to propagation delays (PDs) in uplink transmission from multiple mobile stations (MSs) to an access point (AP) for an orthogonal frequency division multiple access (OFDMA) based mobile communication system. In addition, this paper presents our evaluation of the proposed TAC as applied to dynamic parameter control orthogonal frequency and time division multiple access (DPC-OF/TDMA) which has been suggested for use in new generation mobile communication system. This paper also proposes several formats for an activation slot (ACTS) in which the GIs are lengthened in order to avoid the MAI because the TAC cannot be performed yet in an initial registration of the MSs. Computer simulation elucidates that lengthening the GIs of data symbols in the ACTS adequately to compensate a maximum delay improves the transmission performance of the ACTS at the initial registration without PDs compensation. The simulation also elucidates that the proposed TAC is performed to reduce the influence of the MAI effectively and that updating the estimates of the PDs every certain period is needed to compensate the PDs accurately under high-mobility environment.

This paper proposes an accurate Fast Fourier Transform (FFT) window timing detection method based on the maximum signal-to-interference power ratio (SIR) criterion taking into account the received signal and inter-symbol interference power according to different detected FFT window timings in Orthogonal Frequency and Code Division Multiplexing (OFCDM) wireless access. In the proposed method, the SIR of the received signal is estimated using the desired signal power and inter-symbol interference power calculated based on the power delay profile, which is measured by the cross-correlation between the pilot symbol replica and the received signal. Furthermore, since the SIR is calculated only for the received path timing of the first path and those paths exceeding the guard interval duration, the computational complexity of the proposed method is low. Computer simulation results show that the proposed scheme reduces the required average received signal energy per symbol-to-noise power spectrum density ratio (Es/N0) for achieving the average packet error rate of 10-2 by approximately 1.0 dB compared to the conventional method, which detects the forward path timing of the power delay profile (16QAM data modulation, six-path Rayleigh fading channel, and the maximum delay time of 3 µsec (root mean squared (r.m.s.) delay spread of 0.86 µsec)).

Δ-Timed Atomic Broadcast is the broadcast ensuring that all correct processes deliver the same messages in the same order, and that delivery latency of any message broadcast by any correct process is some predetermined time Δ or less. In this paper, we propose a Δ-timed atomic broadcast algorithm in a synchronous system where communication delay is bounded by a known constant d and processes suffer both crash faults and timing faults. The proposed algorithm can tolerate fc crash faults and ft timing faults as long as at least ft + 1 processes are correct, and its maximum delivery latency Δ is (2f' + 7)d where f' is the actual number of (crash or timing) faulty processes. That is, the algorithm attains the early-delivery in the sense that its delivery latency depends on the actual number of faults rather than the maximum number of faults that the algorithm can tolerate. Moreover, the algorithm has a distinct advantage of guaranteeing that timing-faulty processes also deliver the same messages in the same order as the correct processes (Uniformity). We also investigate the maximum number of faulty processes that can be tolerated. We show that no Δ-timed atomic broadcast algorithm can tolerate ft timing faults, if at most ft processes are correct. The impossibility result implies that the proposed algorithm achieves the maximum fault-resilience with respect to the number of faulty processes.