In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay times of long paths are shortened and the delay times of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which is caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of circuit delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay.

For a baseband pulse amplitude modulation (PAM) signal limited to Nyquist frequency, mathematical derivation of the timing recovery for a fourth-law circuit followed by a band-pass filter is carried out. The results show that the derived timing wave is expressed as a function of the pulse shape entering the timing path and the bandpass filter tuned to the pulse repetition frequency.

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

The detection of timing constraint violation is crucial in reactive systems. A method of detecting deadline violation based on Floyd-Warshall shortest path algorithm has been proposed by Chodrow et al. We extend this method to detect the violation of minimum delay time in reactive systems where the repetition of event sequences frequently occurs.

This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.

In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is O(m2) in the worst-case, where m is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.

In this paper we present two contributions for a set of local transformations (a selection set) to improve a performance of a very large circuit. The first contribution is an idea of "padding node" and "multi-separator-set. " We have proven that combination of padding node and multi-separator-set provides the optimum selection set. The second contribution is our heuristic method to find a semi-optimum multi-separator-set, which uses a network flow algorithm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. We have compared our method with Singh's selection function method, which provides the optimum selection set and is the best method in literature to date. Our method has successfully optimized delays of all circuits, while Singh's selection function method has aborted with three large circuits because of memory overflow. The results also has shown our method has a comparable capability in delay optimization to Singh's method, although our method is heuristic.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.

A symbol timing synchronization method is proposed for the realization of a multi-mode and multi-service software radio receiver. The method enables an accurate search for the optimum symbol timing without any redundant hardware such as sampling rate conversion devices, when the system clock is non-integer times for the target systems' symbol rates. Accordingly, a multimode and multi-service receiver can set an arbitrary system clock for the target systems' symbol rates, and the number of A/D converters can be reduced to the minimum. Also, it may lead to a reduction of the implementation time for digital signal processing hardware, and reduce the burden on the memory in a multi-mode and multi-service software radio receiver, since no sampling rate conversion is needed. The effectiveness of the proposed method for use with a multi-mode and multi-service software radio receiver for future ITS services, which are GPS (Global Positioning System), ETC (Electric Toll Collection system), and Japanese PHS (Personal Handy-phone System) is assumed, and the supposed system is evaluated by computer simulation. The jitter performance under an AWGN (Additive White Gaussian Noise) environment is first simulated, and the necessary number of over-samples and observation symbols are defined by the value of jitter which gives a theoretical value of the BER, respectively. Moreover, the bit error rate performance under a fading environment condition where the attenuation of a signal level fluctuates more rapidly than in a noise environment is calculated, and it is shown that the proposed method enables an accurate search for the optimum synchronization timing caused by a cycle slip even if the signal level is quite low, and allows one handset to adopt a system clock for several systems.

In this paper, we describe statistical properties of timing jitter of symbol timing recovery circuit for carrierless amplitude/phase modulation (CAP)-based very high-rate digital subscriber line (VDSL) system. Analytical expressions of the timing jitter for envelope-based timing recovery system, such as squarer-based timing recovery (S-TR) and absolute-value-based timing recovery (A-TR) schemes, are derived in the presence of additive white Gaussian noise (AWGN) or far-end crosstalk (FEXT). In particular, the analytical and simulation results of the timing jitter performance are presented and compared for a 51.84 Mb/s 16-CAP VDSL system. The A-TR system implemented digitally meets the DAVIC's VDSL system requirement, which specifies the maximum peak-to-peak jitter value of 1.5 nsec and the acquisition time of 20 msec.

In this paper we propose a new timing and phase recovery algorithm to mitigate the inter-symbol interference (ISI) effect and to increase the permissible data rate. We use the mean excess delay of the channel as the timing instant for sampling no matter what symbol rates are transmitted and use the phase of the complex baseband impulse response sampled at the corresponding instant as the carrier phase for compensation. The mean excess delay of a channel is independent of the data transmission rates and can be estimated by the conventional timing recovery circuit by transmitting a low rate data sequence with symbol interval longer than the channel delay spread. We have numerically compared the transmission performances without and with applying our proposed algorithm in the timing and phase recovery. We also compare the transmission performance of the decision feedback equalizer (DFE) when the inputs to the DFE are sampled by the conventional method and by our proposed method. We found that the new scheme has a better performance. Compare with the conventional method, the normalized permissible data rate at a BER threshold of 10-5 and an outage probability of less than 2% can be increased by 5 times. While the new scheme is employed together with DFE, the performance can be further improved. Simulation results for both simulated and physical channels have verified the effectiveness of the new scheme.

We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.

This paper discusses a gate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses on timing uncertainties caused by local random fluctuation. Our method aims to remove both over-design and under-design of a circuit, and realize high-performance and high-reliability LSI design. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method can reduce the delay time further from the circuits optimized for minimizing the delay without the consideration of delay fluctuation.

This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

Multi-cycle paths are paths between registers where 2 or more clock cycles are allowed to propagate signals, and the detection of multi-cycle paths is important in deciding proper clock period, timing verification and logic optimization. This paper presents a satisfiability-based multi-cycle path detection method, where the detection problems are reduced to CNF formulae and the satisfiability is checked using SAT provers. We also show heuristics on conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS'89 benchmarks and other sample circuits. Experimental results show the remarkable improvements on the size of manipulatable circuits.

This letter describes two adaptive timing synchronization schemes for a short-ranged Bluetooth system in the partial-band noise environments. One estimates the variance of the partial-band interference, which is utilized for the trigger threshold value of the inquiry scan and page scan states, while second is designed using the scaled partial correlation value for the connection state. Numerical results show the proposed synchronization algorithms are robust to the partial-band noise interference and of low complexity, which is suitable for a low-cost personal area network (PAN).

Despite their attractive properties, networked virtual environments (net-VEs) are notoriously difficult to design, implement and test due to the concurrency, real-time and networking features in these systems. The current practice for net-VE design is basically trial and error, empirical, and totally lacks formal methods. This paper proposes to apply a Petri net formal modeling technique to a net-VE: NICE (Narrative Immersive Constructionist/Collaborative Environment), predict the net-VE performance based on simulation, and improve the net-VE performance. NICE is essentially a network of collaborative virtual reality systems called CAVE-(CAVE Automatic Virtual Environment). First, we present extended fuzzy-timing Petri net models of both CAVE and NICE. Then, by using these models and Design/CPN as the simulation tool, we have conducted various simulations to study real-time behavior, network effects and performance (latencies and jitters) of NICE. Our simulation results are consistent with experimental data.

A new timing estimation algorithm for asynchronous DS/CDMA multiuser communication system is proposed in this paper. The algorithm is based on the Minimum Variance Distortionless Response (MVDR) beamforming technique that minimizes the beamformer's output power with the constraint that only the signal with exact timing is distortionlessly passed. Exploiting the characteristics that the MVDR beamformer's output power is severely degraded according to erroneous timing estimation, we develop an efficient algorithm to estimate each user's timing by scanning the beamformer's output power variation. Compared to the maximum a posteriori (MAP) or maximum likelihood (ML) based multiuser timing estimator, the complexity is extensively reduced by separating the multi-dimensional optimization problem into several one-dimensional optimization problems. Furthermore, the algorithm is computationally feasible than the subspace-based timing estimator since no eigendecomposition (EVD) is required. Moreover, the proposed algorithm is near-far resistant since the MVDR beamformer is inherently energy independent to the interferers.

A 160 GHz colliding-pulse mode-locked laser diode (CPM-LD) was stabilized by injection of a stable master laser pulse train repeated at a 16th-subharmonic-frequency (9.873 GHz) of the CPM-LD's mode-locking frequency. Synchroscan steak camera measurements revealed a clear pulse train with 16-times repetition frequency of the master laser pulse train for the stabilized CPM-LD output, indicating that CPM-LD output was synchronized to the master laser and that the timing jitter was also reduced. The timing jitter of the stabilized CPM-LD was quantitatively evaluated by an all-optical down converting technique using the nonlinearity of optical fiber. This technique is simple and has a wider bandwidth in comparison to a conventional technique, making it possible to accurately measure the phase noise of ultrafast optical pulse train when its repetition frequency exceeds 100 GHz. The electrical power spectra measurements indicated that the CPM-LD's mode-locking frequency was exactly locked by the injection of the master laser pulse train and that the timing jitter decreased as the injection power increased. The timing jitter was reduced from 2.2 ps in free running operation to 0.26 ps at an injection power of 57 mW, comparable to that of the master laser (0.21 ps).