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39181-39200hit(42756hit)

  • An Extension to the Overfitting Lattice Filter for ARMA Parameter Estimation with Additive Noise

    Marco A. Amaral HENRIQUES  Md. Kamrul HASAN  Takashi YAHAGI  

     
    LETTER-Speech

      Vol:
    E76-A No:3
      Page(s):
    480-482

    This letter extends the overfitting lattice filter for ARMA parameter estimation with additive noise proposed by Sun and Yahagi. A new way of calculating the lattice parameters is proposed, making their computation truly recursive. This simplifies the method in Ref.(1), and makes it suitable to the parameter estimation of high-order systems.

  • Multiple-Valued Memory Using Floating Gate Devices

    Takeshi SHIMA  Stephanie RINNERT  

     
    PAPER

      Vol:
    E76-C No:3
      Page(s):
    393-402

    This paper discusses multiple-valued memory circuit using floating gate devices. It is an object of the paper to provide a new and improved analog memory device, which permits the memory of an amount of charges that accurately corresponds to analog information to be stored.

  • Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Graph

    Tsuyoshi ISSHIKI  Yoshinori TAKEUCHI  Hiroaki KUNIEDA  

     
    PAPER

      Vol:
    E76-A No:3
      Page(s):
    337-348

    In this paper, a methodology for designing the architecture of the processor array for wide class of image processing algorithms is proposed. A concept of spatially expanding the SFG description which enables us to handle the problem as merely one-dimensional signal processing is used in constructing the methodology. Problem of I/O interface which is critical in real-time processing is also considered.

  • FOREWORD

    Shuji TSUKIYAMA  Tatsuo OHTSUKI  

     
    FOREWORD

      Vol:
    E76-A No:3
      Page(s):
    257-258
  • Some EXPTIME Complete Problems on Context-Free Languages

    Takumi KASAI  Shigeki IWATA  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E76-D No:3
      Page(s):
    329-335

    Some problems in formal language theory are considered and are shown to be deterministic exponential time complete. They include the problems for a given context-free grammar G, a nondeterministic finite automaton M, a deterministic pushdown automaton MD, of determining whether L(G)L(M), and whether L(MD)L(M). Polynomial time reductions are presented from the pebble game problem, known to be deterministic exponential time complete, to each of these problems.

  • Periodic Responses of a Hysteresis Neuron Model

    Simone GARDELLA  Ryoichi HASHIMOTO  Tohru KUMAGAI  Mitsuo WADA  

     
    PAPER-Bio-Cybernetics

      Vol:
    E76-D No:3
      Page(s):
    368-376

    A discrete-time neuron model having a refractory period and containing a binary hysteresis output function is introduced. A detailed mathematical analysis of the output response is carried out and the necessary and sufficient condition which a sequence must satisfy in order to be designated as a periodic response of the neuron model under a constant or periodic stimulation is given.

  • Architecture and Mechanism of the Control and OAM Information Transport Network Using a Distributed Directory System

    Laurence DEMOUNEM  Hideaki ARAI  Masatoshi KAWARASAKI  

     
    PAPER

      Vol:
    E76-B No:3
      Page(s):
    291-303

    The current telecommunication network is structured in two layers: The intelligent layer that includes Intelligent Network (IN) nodes and Operation, Administration and Maintenance (OAM) nodes, and the transport layer that includes Network Elements (NEs). The transport layer carries user Information (Iu) from end-users as well as control and OAM Information (Ic&o) from IN/OAM nodes. The quick deployment of new IN services and OAM capabilities that will need (a) flexibility and easy management, and (b) an effective handling method for searching the huge amount of data among distributed databases, will be two requirements to be satisfied. Integrating various types of Ic&o into a unique Ic&o transport network and using ATM technique as a transport technique satisfies partly the requirement (a). To completely meet both requirements, this paper proposes the following solutions:(a) Intelligent layer connections and transport layer connections should be managed independently: The necessary mapping between the Logical Destination Address (LDA) that represents the logical address of the physical entity where data are routed, combined with the Quality Of Service (QOS) type, and the ATM connection IDentifier (ID), that is to say the Virtual Channel Identifier/ Virtual Path Identifier (VCI/VPI), is provided by specific nodes (the Ic&o network Management Nodes (Ic&o MNs)) belonging to an intermediate layer, i.e., the Ic&o network management layer.(b) The widely distributed aspect of the databases also needs a very effective data handling method. This paper proposes to implement a Distributed Directory System (DDS) into both intelligent nodes and Ic&o MNs.In order to apply the DDS function to 2 functional levels, the following items are studied: First, the possible mapping of DDS functions into the intelligent node functions is proposed. Second, this paper gives an interaction scenario between intelligent nodes and Ic&o MNs, to translate the LDA/QOS type into VPI/VCI. Finally, the analysis of the mapping of LDA/QOS type into VCI/VPI at the ATM level shows that the Ic&o network based on VP backbone offers the best compromise between flexibility, complexity and cost.

  • On Precision of Solutions by Finite-Difference Time-Domain Method of Different Mesh Spacings

    Masao KODAMA  Mitsuru KUNINAKA  

     
    LETTER-Antennas and Propagation

      Vol:
    E76-B No:3
      Page(s):
    315-317

    When we study time-domain electromagnetic fields, we frequently use the finite-difference time-domain (FD-TD) method. In this paper, we discuss errors of the FD-TD method and present the optimum mesh spacings in the FD-TD method when the three mesh spacings are different.

  • Priority Management to Improve the QOS in ATM Networks

    Tien-Yu HUANG  Jean-Lien Chen WU  Jingshown WU  

     
    PAPER

      Vol:
    E76-B No:3
      Page(s):
    249-257

    Broadband ISDN, using asynchronous transfer mode, are expected to carry traffic of different classes, each with its own set of traffic characteristics and performance requirements. To achieve the quality of service in ATM networks, a suitable buffer management scheme is needed. In this paper, we propose a buffer management scheme using a priority service discipline to improve the delay time of delay-sensitive class and the packet loss ratio of loss-sensitive class. The proposed priority scheme requires simple buffer management logic and minor processing overhead. We also analyze the delay time and the packet loss ratio for each class of service. The results indicate that the required buffer size of the proposed priority scheme is reduced and the delay time of each class of service is controlled by a parameter. If the control parameter is appropriately chosen, the quality of service of each class is improved.

  • A Novel Design of Very Low Sensitivity Narrow-Band Band-Pass Switched-Capacitor Filters

    Sin Eam TAN  Takahiro INOUE  Fumio UENO  

     
    PAPER

      Vol:
    E76-A No:3
      Page(s):
    310-316

    In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

  • The Body Fitted Grid Generation with Moving Boundary and Its Application for Optical Phase Modulation

    Michiko KURODA  Shigeaki KURODA  

     
    PAPER-Electromagnetic Theory

      Vol:
    E76-C No:3
      Page(s):
    480-485

    In a coherent optical communication system, a polarization fluctuation of an optical fiber is one of the most important problem. On the other hand, for a realization of optical devices, dielectric waveguides with sinusoidally varying width are investigated. Knowledge of the electromagnetic field distribution in a dielectric waveguide with boundary perturbed time by time becomes a very interesting problem. This paper shows a numerical method to simulate the effect of the external disturbance against the dielectric waveguide from time to time. The author has discussed body fitted grid generation with moving boundary for the Poisson's equation and the Laplace's equation. Here we apply this theory for the dielectric waveguide. The technique employs a kind of an expanded numerical grid generation. As the author added time component to grid generation, the time dependent coordinate system which coincides with a contour of moving boundary could be transformed into fixed rectangular coordinate system. Two cases of the perturbations against the dielectric waveguide are treated. In the first case, we present the electric distribution in the dielectric waveguide perturbed along a propagation path. While in the second case, the electric field in the waveguide perturbed perpendicular to the propagation path. Such phenomena that the phase of the electric field modulated by the external perturbation are clarified by numerical results. This technique makes it possible not only to analyze the effect of the external disturbance in a coherent optical communication system but also to fabricate optical modulators or couplers.

  • Considerations on Future Customer Premises Network

    Takeo FUKUDA  Toshikazu KODAMA  Yasuhiro KATSUBE  

     
    PAPER

      Vol:
    E76-B No:3
      Page(s):
    213-219

    Broadband ISDN based on ATM technologies is expected to offer enhanced and sophisticated services to customers. Since ATM will first be introduced in the business communication world, it will be worth to discuss the future image of desirable ATM customer premises network (CPN). In this paper, we first consider the possible migration scenario of Broadband CPN and some important requirements for the realization of the scenario. Then, we discuss the key issues to be solved for future ATM-CPN, which include network topology, traffic control and connectionless communication services.

  • Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation

    Takeshi KASUGA  Michitaka KAMEYAMA  Tatsuo HIGUCHI  

     
    PAPER

      Vol:
    E76-C No:3
      Page(s):
    428-435

    Robust-fault tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of faults in digital system. There are many cases where the safety of digital control systems can be maintained if the property is satisfied. In this paper, robust-fault-tolerant three-valued arithmetic modules such as an adder and a multiplier are proposed. The positive and negative integers are represented by the number of 1's and 1's, respectively. The design concept of the arithmetic modules is that a fault makes linearly additive effect with a small value to the final result. Each arithmetic module consists of identical submodules linearly connected, so that multi-stage structure is formed to generate the final output from the last submodule. Between the input and output digits in the submodule some simple functional relation is satisfied with respect to the number of 1's and 1's. Moreover, the output digit value depends on very small portion of the submodules including the input digits. These properties make the linearly additive effect with a small value to the final result in the arithmetic modules even if multiple faults are occurred at the input and output of any gates in the submodules. Not only direct three-valued representation but also the use of three-valued logic circuits is inherently suitable for efficient implementation of the arithmetic VLSI system. The evaluation of the robust-fault-tolerant three-valued arithmetic modules is done with regard to the chip size and the speed using the standard CMOS design rule. As a result, it is made clear that the chip size can be greatly reduced.

  • An Overall Analysis of Periodically Time Varying Digital Filters

    Xiong Wei MIN  Rokuya ISHII  

     
    PAPER-Digital Signal Processing

      Vol:
    E76-A No:3
      Page(s):
    425-438

    The main interest of this paper is the theoretical analysis of a recursive periodically time varying digital filter. The generalized transfer function of a recursive periodically time varying digital filter was obtained from its difference equation. It was proved that by making use of the generalized transfer function, we can not only derive the input and output relationship of a recursive periodically time varying digital filter easily but also obtain its equivalent structure effectively. An interesting property of a recursive periodically time varying digital filter was also derived by making use of its generalized transfer function. Moreover, it was completed in this paper the investigation of the generalized transfer functions and impulse responses of other periodically time varying models, including an input sampling polyphase model and an output sampling polyphase model. Meanwhile, the multirate Quadrature Mirror Filter bank system was proved by the authors to be a periodically time varying system. Several examples were also provided to illustrate the effectiveness of using the generalized transfer function to obtain the equivalent structure of a recursive periodically time varying digital filter.

  • LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations

    Masakazu KATO  Masayoshi SAKAI  Koji JINKAWA  Koichi FUTSUHARA  Masao MUKAIDONO  

     
    PAPER

      Vol:
    E76-C No:3
      Page(s):
    419-427

    A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.

  • A New kth-Shortest Path Algorithm

    Hiroshi MARUYAMA  

     
    LETTER-Algorithm and Computational Complexity

      Vol:
    E76-D No:3
      Page(s):
    388-389

    This paper presents a new algorithm for finding the kth-shortest paths between a specified pair of vertices in a directed graph with arcs having non-negative costs.

  • Construction Techniques for Error-Control Runlength-Limited Block Codes

    Yuichi SAITOH  Takahiro OHNO  Hideki IMAI  

     
    PAPER-Information Theory and Coding Theory

      Vol:
    E76-A No:3
      Page(s):
    453-458

    A technique is presented for constructing (d,k) block codes capable of detecting single bit errors and single peak-shift errors in consecutive two runs. This constrains the runlengths in the code sequences to odd numbers. The capacities and the cardinalities for finite code length of these codes are described. A technique is also proposed for constructing (d,k) block codes capable of correcting single peak-shift errors.

  • FOREWORD

    Hidetoshi KIMURA  Tetsuya MIKI  Yuji INOUE  Yasushi WAKAHARA  Koso MURAKAMI  Chihaya TANAKA  

     
    FOREWORD

      Vol:
    E76-B No:3
      Page(s):
    211-212
  • Multimedia "Paper" Services/Human Interfaces and Multimedia Communication Workstation for Broadband ISDN Environments

    Tsuneo KATSUYAMA  Hajime KAMATA  Satoshi OKUYAMA  Toshimitsu SUZUKI  You MINAKUCHI  Katsutoshi YANO  

     
    PAPER

      Vol:
    E76-B No:3
      Page(s):
    220-228

    Broadband multimedia information environments are part of the next big advance in communications and computer technology. The use of multimedia infrastructures in offices is becoming very important. This paper deals with a service concept and human interfaces based on a paper metaphor. The proposed service offers the advantages of paper and eliminates the disadvantages. The power of multimedia's expressiveness, user interaction, and hypermedia technology are key points of our solution. We propose a system configuration for implementing the service/human interface.

  • Timing Optimization of Multi-Level Networks Using Boolean Relations

    Yuji KUKIMOTO  Masahiro FUJITA  

     
    PAPER

      Vol:
    E76-A No:3
      Page(s):
    362-369

    In this paper we propose a new timing optimization technique for multi-level networks by restructuring multiple nodes simultaneously. Multi-output subcircuits on critical paths are extracted and resynthesized so that the delays of the paths are reduced. The complete design space of the subcircuits is captured by Boolean relations, which allow us to perform more powerful resynthesis than previous approaches using don't cares. Experimental results are reported to show the effectiveness of the proposed technique.

39181-39200hit(42756hit)