The method of estimating multiple sound source locations based on a neural network algorithm and its performance are described in this paper. An evaluation function is first defined to reflect both properties of sound propagation of spherical wave front and the uniqueness of solution. A neural network is then composed to satisfy the conditions for the above evaluation function. Locations of multiple sources are given as exciting neurons. The proposed method is evaluated and compared with the deterministic method based on the Hyperbolic Method for the case of 8 sources on a square plane of 200m200m. It is found that the solutions are obtained correctly without any pseudo or dropped-out solutions. The proposed method is also applied to another case in which 54 sound sources are composed of 9 sound groups, each of which contains 6 sound sources. The proposed method is found to be effective and sufficient for practical application.

BiCMOS circuit performance at low supply voltages is discussed. The basic advantages of BiCMOS circuits are briefly reviewed, and then actual advantages of the BiCMOS gate and the BiCMOS sense circuits, which are typical BiCMOS circuits, are explained. Their advantages at low supply voltages are also discussed. BiCMOS gates, BiCMOS sense circuits, and combined circuits that include a BiCMOS sense circuit are two or three times faster than CMOS circuits down to a supply voltage of 2 V. BiCMOS circuits have high performance even at low supply voltages such as 2 V.

A low-voltage, high-speed 4-bit CMOS single chip microprocessor, with instruction execution time of 1.0µs at a power supply voltage of 1.8V, has been developed. A single chip processor generally includes crystal oscillation circuits to generate a system clock or a time-base clock. But when the operating voltage is lowered, it becomes difficult to get oscillations to start reliably and to continue stably. This paper describes a low voltage circuit design method for built-in crystal oscillators. Simple design equations for oscillation starting voltage and oscillation starting time are introduced. Then effects of the circuit device parameters, such as power supply voltage, loop gain values, and subthreshold swing S, on the low voltage performance of the crystal oscillators are considered. It is shown that the crystal oscillators operate in a tailing (subthreshold) region at voltages lower than about 1.8 V. Subthreshold swing, threshold voltage, and open loop gain have a significant influence on low voltage oscillation capability. This design method can be applied to crystal oscillators for a wide range of operating voltages.

This paper proposes a self frequency preset (SFP) PLL synthesizer to realize a simple frequency preset PLL synthesizer with temperature-resistant and shorter frequency settling time than the conventional temperature un-compensated phase and frequency preset (PFP) PLL synthesizer. Since the proposed synthesizer employs a simple frequency locked loop (FLL) circuit to preset the output frequency at each frequency hopping period, the synthesizer eliminates the need to store f-V characteristic of the VCO in ROM. The frequency settling time of the proposed synthesizer is theoretically and experimentally analyzed. The theoretical analysis using the realistic f-V characteristic of a IF band VCO show that the frequency settling time of the proposed synthesizer is 130µs shorter than that of the conventional PFP PLL synthesizer at 40MHz hopping in the 200MHz band for all temperatures. Furthermore, the experimental results confirm that the frequency acquisition time of a prototype FLL circuit is accordant with the calculated results. Thus, the proposed SFP PLL synthesizer can achieve faster frequency settling than the conventional PFP PLL synthesizer for all temperatures and its simple configuration allows to be easily implemented with existing CMOS ASIC devices.

Recently, fuzzy logic which is a kind of infinite multiple-valued logic has been studied to treat certain ambiguities, and its algebraic properties have been studied by the name of fuzzy logic functions. In order to treat modality (necessity, possibility) in fuzzy logic, which is an important concept of multiple-valued logic, the intuitionistic logical negation is required in addition to operations of fuzzy logic. Infinite multiple-valued logic functions introducing the intuitionistic logical negation into fuzzy logic functions are called Kleene-Stone logic functions, and they enable us to treat modality. The domain of modality in which Kleene-Stone logic functions can handle, however, is too limited. We will define α-KS logic functions as infinite multiple-valued logic functions using a unary operation instead of the intuitionistic logical negation of Kleene-Stone logic functions. In α-KS logic functions, modality is closer to our feelings. In this paper we will show some algebraic properties of α-KS logic functions. In particular we prove that any n-variable α-KS logic function is determined uniquely by all inputs of 7 values which are 7 specific truth values of the original infinite truth values. This means that there is a bijection between the set of α-KS logic functions and the set of 7-valued α-KS logic functions which are restriction of α-KS logic functions to 7 specific truth values. Finally, we show a necessary and sufficient condition for a 7-valued logic function to be a 7-valued α-KS logic function.

A 155-Mb/s 3232 Si bipolar switch LSI is designed and implemented for a wide application in the broad-band ISDN. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies are newly developed for the LSI, namely, 1) active pull-down circuit with an embedded bias circuit in each gate, and 2) modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area are reduced to 60% and 70%, respectively, of what is expected when conventional ECL technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system.

This paper addresses onboard processing architecture employing direct regeneration. The advantage of direct regeneration is its hardware simplicity, even though the bit error rate performance is slightly inferior to that of demodulation-remodulation scheme with coherent detection. The channel filtering schemes as well as achievable capacities are examined by computer simulation. It is found that the system with direct regeneration has advantage in channel capacity and transmit earth station e.i.r.p. for small earth stations. A possible configuration of direct regeneration onboard in future satellite systems is proposed.

A new bus architecture is proposed for reducing the operating power of future ULSI's. This architecture will relieve the constraint of the conventional supply voltage scaling, which makes it difficult to achieve both high speed and a low standby current if the supply voltage is scaled to less than 2 V. It employs new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration through the use of low-VT MOSFET's and an internal supply voltage corresponding to the reduced signal swing. Bus delay is almost halved with this driver when operated at 0.6-V swing and 2-V supply. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of new bus driver and bus receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining a high-speed data transmission and a low standby current. A test circuit is designed and fabricated using 0.3-µm processes. The operation of the proposed architecture was verified, and further improvements in the speed performance are expected by device optimization. The proposed architecture is promising for reducing the operating power of future ULSI's.

Using a CCD/CMOS technology, a fully parallel 4 4 focal plane processor, which performs image acquisition, smoothing, and segmentation, had been fabricated and characterized. In this chip, image brightness is converted into signal charge using CCD imaging techniques. The Gaussian smoothing operation is approximated by the repeated application of a simple nearest neighbor binomial convolution mask, realizing the first known use of a true two-dimensional charge division and transfer process. The design allows full control of the spatial extent of the smoothing operation, and incorporates segmentation circuits with global variable threshold control at each pixel location to preserve edges in the image. The processed image is read out using a standard CCD clocking scheme.

This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor Vbe matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm2 chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz ft, double-polysilicon self-aligned bipolar technology.

Under the conditions of Poisson arrivals and single copy transmission, we designed a minimum delay protocol for packet satellite communications. The approach is to assume a hybrid random-access/reservation protocol, derive its average delay and minimize the delay with respect to all tunable system parameters. We found that for minimum average delay,1) a spare reservation should normally but not always be made for each packet transmission.2) all unreserved slots (i.e. Aloha slots) should be filled with a packet rate of one per slot whenever possible. In other words, the utilization of Aloha slots should be maximized.3) an optimum balance between transmitting packets and making reservations before transmission should be maintained.

This paper discusses psychophysical aspects of human sensory system through a differential-geometrical formulation. The discussions reveal relationships among three fundamental functions--the psychophysical, the DL and the JND functions, which characterize sensory system.

The Hilbert curve is one of the simplest curves which pass through all points in a space. Many researchers have worked on this curve from the engineering point of view, such as for an expression of two-dimensional patterns, for data compression in an image or in color space, for pseudo color image displays, etc. A computation algorithm of this curve is usually based on a look-up table instead of a recursive algorithm. In such algorithm, a large memory is required for the path look-up table, and the memory size becomes proportional to the image size. In this paper, we present an implementation of a fast sequential algorithm that requires little memory for two and three dimensional Hilbert curves. Our method is based on some rules of quad-tree traversal in two dimensional space, and octtree traversal in three dimensional space. The two dimensional Hilbert curve is similar to the scanning of a DF (Depth First) expression, which is a quad-tree expression of an image. The important feature is that it scans continuously from one quadrant, which is obtained by quad tree splitting, to the next adjacent one in two dimensional space. From this point, if we consider run-lengths of black and white pixels during the scan, the run-lengths of the Hilbert scan tend to be longer than those of the raster scan and the DF expression scanning. We discuss the application to data compression using binary images and three dimensional data.

Surface reconstruction and visualization from sparse and incomplete surface data is a fundamental problem and has received growing attention in both computer vision and graphics. This paper presents a computational scheme for realistic visualization of free-formed surfaces from 3D range images. The novelty of this scheme is that by integrating computer vision and computer graphics techniques, we dynamically construct a mesh representation of the arbitrary view of the surfaces, from a view-invariant shape description obtained from 3D range images. We outline the principle of this scheme and describle the frame work of a graphical reconstruction model, we call arbitrarily oriented meshes', which is developed based on differential geometry. The experimental results on real range data of human faces are shown.

We propose a high-speed SOI bipolar transistor fabricated using bonding and thinning techniques. It is important to replace SOI area except for devices with thick SiO2 to reduce parasitic capacitance. A thin SOI film with a thin buried layer helps meet this requirement. We formed a 1-µm-thick SOI film with a 0.7-µm-thick buried layer by ion implantation before wafer bonding pulse-field-assisted bonding and selective polishing. Devices were completely isolated by thick SiO2 using a thin SOI film and the LOCOS process. We fabricated epitaxial base transistors (EBTs) on bonded SOI. Our transistors had a cutoff frequency of 32 GHz.

In this paper, we propose an algorithm of O(|V|min{k,|V|,|A|}|A|) time complexity for finding all k-edge-connected components of a given digraph D=(V,A) and a positive integer k. When D is symmetric, incorporating a preprocessing reduces this time complexity to O(|A|+|V|2+|V|min{k,|V|}min{k|V|,|A|}), which is at most O(|A|+k2|V|2).

A new redundancy technique especially suitable for ultra-high-speed static RAMs (SRAMs) has been developed. This technique is based on a decoding-method that uses two kinds of fuses without introducing any additional delay time. One fuse is initially ON and can be turned OFF afterwards, if necessary, by a cutting process using a focused ion beam (FIB). The other is initially OFF and can be turned ON afterwards by a connecting process using laser chemical vapor deposition (L-CVD). This technique is applied to a 64 kbit SRAM having a 1.5-ns access time. The experimental results obtained through an SRAM chip repaired using this redundancy technique show that this technique does not introduce any increase in the access time and does not reduce the operational margin of the SRAM.

In this work, we introduce a fuzzy inference in conventional backpropagation learning algorithm, for networks of neuron like units. This procedure repeatedly adjusts the learning parameters and leads the system to converge at the earliest possible time. This technique is appropriate in a sense that optimum learning parameters are being applied in every learning cycle automatically, whereas the conventional backpropagation doesn't contain any well-defined rule regarding the proper determination of the value of learning parameters.

Correspondence based on regions rather than lines seems to be effective, as regions are usually fewer than other image features and provide global information such as size, color, adjacency, etc. In this paper, we present a region matching approach for solving the correspondence problem. Images are segmented into regions and are individually described by classification tables using region adjacencies. From the structural description of the two images, the region matching process based on color and structural similarity is carried out. First, a small number of significant regions are selected and matched by using color, and then they are used as handles for constraint propagation to match the remaining regions by using structures. Our technique was implemented by using an efficient selection and propagation algorithm and was tested with a variety of scenes.