By optimizing the structure of erbium-doped fibers, high efficiency such as a gain coefficient of 6.3dB/mW, or a slope efficiency of 92.6% have been realized with very flat wavelength dependence. Though the optimized structure has high NA, the splice loss with standard fibers can be lowered by the additional arc technique. The carbon coated fiber with a fatigue parameter over 150 guarantees the reliability, even when wounded on a small coil. In-line isolators and WDM couplers have been also developed. An amplifier module has been assembled, resulting in an output power more than +16dBm owing to the high performance of each component.

This paper describes the potential of KrF excimer laser lithography for the development and production of 64 M and 256 Mbit DRAMs on the basis of our recent developed results. Quarter micron KrF excimer laser lithography has been developed. A new chemically amplified positive resist realizes high stability and process compatibility for 0.25 micron line and space patterns and 0.35 micron contact hole patterns. This developed resist is characterized as the increase of dissolution characteristics in exposed areas, and hence means the high resolution is obtained. A multiple interference effect was greatly reduced by using our over coat film or anti-reflective coating. This over coat film has no intermixing to the resist and it is simultaneously removed when the resist is developed. This anti-reflective coating has low etch selectivity to the resist, and hence the over coat film is etched away when etching the substrate. The two major results indicate that the KrF excimer laser lithography is promising for the development of 256 MDRAMs.

A new technique for evaluating gate oxide reliability using photon emission method has been developed. This method enables the measurements of the initial breakdown characteristics, reliability testing and failure analysis consistently. From the experimental results, followings are clarified for the first time using this technique. Failure modes in the initial characteristics have close correlation to TDDB characteristics and both characteristics correspond to the location of breakdown spot. The results suggest measures to improve the reliability of gate oxide and the existance of new failure mechanism.

Two kinds of nitrided ultrathin (510 nm) SiO2 films were formed on the silicon (100) face using rapid thermal NH3-nitridation (RTN) and rapid thermal N2O-oxynitridation (RTON) technologies. The MOS capacitors with RTN SiO2 film showed that by Fowler-Nordheim (F-N) electron injection, both electron trap density and low-field leakage increase by the NH3-nitridation. In addition, the charge-to-breakdown (QBD) value decreases owing to NH3-nitridation. By contrast, RTON SiO2 films exhibited extremely low electron trap density, almost no increase of the leakage current, and large QBD value above 200C/cm2. The oxide film composition was evaluated by secondary ion mass spectroscopy (SIMS). The chemical bonding states were also examined by Fourier transform-infrared reflection attenuated total reflectance (FT-IR ATR) and X-ray photoelectron spectroscopy (XPS) measurements. These results indicate that although a large number of nitrogen (N) atoms are incorporated by the RTN and RTON, only the RTN process generates the hydrogen-related species such as NH and SiH bounds in the film, whereas the RTON film indicates only SiN bonds in bulk SiO2. From the dielectric and physical properties of the oxide films, it is considered that the oxide wearout by high-field stress is the result of the electron trapping process, in which anomalous leakage due to trap-assisted tunneling near the injected interface rapidly increases, leading to irreversible oxide failure.

The path diversity improvement inherent in direct sequence spread spectrum (DS/SS) signalling under multi-path propagation environments is investigated for mobile/personal radio communications systems that employ DPSK modulation. The bit error rate (BER) performance of post-demodulation selection diversity reception is theoretically analyzed in the presence of noise-only-paths in the time window for diversity combining. Results of laboratory experiments conducted to evaluate the BER performance are also presented. It is shown that the experimental results agree well with the theoretical BER.

The effects of low temperature etching for sub-half micron multi-layer resist are investigated. The low temperature etching with pure O2 gas provides higher anisotropic profiles than with an additional gas such as Cl2, N2. This is caused by the difference in the formative process of the side wall protection. With pure O2 gas at 80, highly anisotropic profiles for 0.35 µm patterns can be performed while the maximum tolerable width loss is below 0.03 µm.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.

Self-aligned aluminum-gate MOSFET's have been successfully fabricated by employing ultraclean ion implantation technology. The use of ultra high vacuum ion implanter and the suppression of high-energy ion-beam-induced metal sputter contamination have enabled us to form ultra-shallow low-leakage pn junctions by furnace annealing at a temperature as low as 450. The fabricated aluminum-gate MOSFET's have exhibited good electrical characteristics, thus demonstrating a large potential for application to realizing ultra-high-speed integrated circuits.

Improvement of fatigue behavior of a fusion spliced portion on a carbon-coated fiber is achieved by recoating carbon using a thermal-CVD process with a CO2 laser as a local heat source. The fatigue parameters, so-called n-values, of 121 and 94 are obtained on the non-spliced portion and the spliced portion, respectively. Assuming a life time prediction model, these high values have been proved to have an advantage in a long-term reliability and to be sufficient in a practical submarine cable use.

A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N+ and the P+ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.

The subject of the paper is to propose an O(|V|+|E|) algorithm for the 3-edge-connectivity augmentation problem (UW-3-ECA) defined by "Given an undirected graph G0=(V,E), find an edge set E of minimum cardinality such that the graph (V,EE ) (denoted as G0+E ) is 3-edge-connected, where each edge of E connects distinct vertices of V." Such a set E is called a solution to the problem. Let UW-3-ECA(S) (UW-3-ECA(M), respectively) denote UW-3-ECA in which G0+E is required to be simple (G0+E may have multiple edges). Note that we can assume that G0 is simple in UW-3-ECA(S). UW-3-ECA(M) is divided into two subproblems (1) and (2) as follows: (1) finding all k-edge-connected components of a given graph for every k3, and (2) determining a minimum set of edges whose addition to G0 result in a 3-edge-connected graph. Concerning the subproblem (1), we use an O(|V|+|E|) algorithm that has already been existing. The paper proposes an O(|V|+|E|) algorithm for the subproblem (2). Combining these algorithms makes an O(|V|+|E|) algorithm for finding a solution to UW-3-ECA(M). Furthermore, it is shown that a solution E to UW-3-ECA(M) is also a solution to UW-3-ECA(S) if |V|4, partly solving an open problem UW-k-ECA(S) that is a generalization of UW-3-ECA(S).

The performance of copper interconnects formed by the low-kinetic-energy ion bombardment process has been investigated. The copper films formed on SiO2 by this technology under a sufficient amount of ion energy deposition exhibit perfect orientation conversion from Cu (111) to Cu (100) upon post-metallization thermal annealing. We have discovered such crystal orientation conversion is always accompanied by a giant-grain growth as large as 100 µm. The copper film resistivity decreases due to the decrease in the grain boundary scattering, when the giant-grain growth occurs in the film. The resistivity of giant-grain copper film at a room temperature is 1.76 µΩcm which is almost equal to the bulk resistivity of copper. Furthermore, a new-accelerated electromigration life-test method has been developed to evaluate copper interconnects having large electromigration resistance within a very short period of test time. The essence of the new method is the acceleration by a large-current-stress of more than 107 A/cm2 and to utilize the self heating of test interconnect for giving temperature stress. In order to avoid uncontrollable thermal runaway and resultant interconnect melting, we adopted a very efficient cooling system that immediately removes Joule heat and keeps the interconnect temperature constant. As a result, copper interconnects formed by the low-kinetic-energy ion bombardment process exhibit three orders of magnitude longer lifetime at 300 K than Al alloy interconnects.

We designed and fabricated a prototype 0.4-µm-gate CMOS/SIMOX PLL LSI in order to verify the potential usefulness of ultrathin-film SIMOX technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. This PLL LSI contains both high-frequency components such a prescaler and low-frequency components such as a shift register, phase frequency comparator, and fixed divider. One application of the LSI could be for synthesizing communication band frequencies in the front-end of a battery-operated wireless handy terminal for personal communications. At a supply voltage of 2 V, this LSI operates at up to 2 GHz while dissipating only 8.4 mW. Even at only 1.2 V, 1 GHz-operation can be obtained with a power consumption of merely 1.4 mW. To explain this low-power feature, we extensively measured the electrical characteristics of individual CMOS/SIMOX basic circuits as well as transistors. Test results showed that the high performance of the LSI is mainly due to the advanced nature of the CMOS/SIMOX devices with low parasitic capacitances around source/drain regions and to the new circuit design techniques used in the dual-modulus prescalar.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.

A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.

We report on Brillouin optical-fiber time domain reflectometry (BOTDR) for distributed temperature or strain measurement along a single-mode optical fiber. BOTDR uses Brillouin scattering in optical fibers, whose Brillouin frequency shift increases in proportion to temperature or strain induced in the fiber. This method requires access to only one end of a fiber, as with conventional optical time domain reflectometry (OTDR) which uses Rayleigh scattering in optical fibers. In BOTDR, a coherent optical detection method is used as a backscattered light detection technique. This technique can achieve both high sensitivity and high frequency resolution and easily separate a weak Brillouin line from a strong Rayleigh scattering peak and Fresnel reflected light. Experimental results show the potential for measuring temperature and strain distribution with respective accuracies of 3 or 0.006%, and a spatial resolution of 100m in an 11.57km long fiber.

We propose an integrated smart cable operation system and its architecture for the future cable network. In the proposed architecture, an application programs and various modules are loosely coupled using a cable operation system platform. We anticipate the task flows for the future optical cable network operation in order to realize the proposed system and architecture. Each task flow is broken down into "atomic tasks." The task flow can be changed easily by combining these atomic tasks. We use an object-oriented design for designing the cable operation system platform. As a first step towards the construction of the proposed system a pre-prototype system was constructed and the results are shown.

This paper proposes a surveillance system concept, which includes the analysis of fiber fault factors and monitored items, the architecture for diagnosing fiber degradation and the system configuration. Fiber faults are classified into two types. One is fiber failure caused by fiber axial tensile strain and the other is fiber loss increase caused by fiber bending and the absorption of hydrogen molecules. It was found that there is an urgent need for fiber axial strain monitoring, sensitive loss monitoring operating at longer wavelengths and water sensing, in order to detect the origin and early indications of these faults before the service is affected. Moreover, an algorithm for predicting and diagnosing fiber faults based on the detected results was investigated and systematized.

Optical soliton transmissions at 10 and 20Gbit/s over 1000km with the use of erbium-doped fiber amplifiers are described in detail. For the 10Gbit/s experiment, a bit error rate (BER) of below 110-13 was obtained with 220-1 pseudorandom patterns and the power penalty was less than 0.1dB. In the 20Gbit/s experiment optical multiplexing and demultiplexing techniques were used and a BER of below 110-12 was obtained with 223-1 pseudorandom patterns under a penalty-free condition. A new technique for sending soliton pulses over ultralong distances is presented which incorporates synchronous shaping and retiming using a high speed optical modulator. Some experimental results over 1 million km at 7.210Gbit/s are described. This technique enables us to overcome the Gordon-Haus limit, the accumulation of amplified spontaneous emission (ASE), and the effect of interaction forces between adjacent solitons. It is also shown by computer runs and a simple analysis that a one hundred million km soliton transmission is possible by means of soliton transmission controls in the time and frequency domains. This means that limit-free transmission is possible.