A speech analysis/synthesis system that relies on a time-varying Auto Regressive Moving Average (ARMA) process and the Short-Time Fourier Transform (STFT) is proposed. The narrowband components in speech are represented in the frequency domain by a set of harmonic components, while the broadband random components are represented by a time-varying ARMA process. The time-varying ARMA model has a dual function, namely, it creates a spectral envelope that fits accurately the harmonic STFT components, and provides for the spectral representation of the broadband components of speech. The proposed model essentially combines the features of waveform coders by employing the STFT and the features of traditional vocoders by incorporating an appropriately shaped noise sequence.

It is shown from a computer analysis that there exists a resonant mode of a surface wave which propagates along Goubau line, and that the attenuation of such a mode is very low. The approximate formula for obtaining the resonant frequency is also given.

We have proposed a new omnidirectional image sensor COPIS (COnic Projection Image Sensor) for guiding navigation of a mobile robot. Its feature is passive sensing of the omnidirectional image of the environment in real-time (at the frame rate of a TV camera) using a conic mirror. COPIS is a suitable sensor for visual navigation in real world environment with moving objects. This paper describes a method for estimating the location and the motion of the robot by detecting the azimuth of each object in the omnidirectional image. In this method, the azimuth is matched with the given environmental map. The robot can always estimate its own location and motion precisely because COPIS observes a 360 degree view around the robot even if all edges are not extracted correctly from the omnidirectional image. We also present a method to avoid collision against unknown obstacles and estimate their locations by detecting their azimuth changes while the robot is moving in the environment. Using the COPIS system, we performed several experiments in the real world.

In this work, we introduce a fuzzy inference in conventional backpropagation learning algorithm, for networks of neuron like units. This procedure repeatedly adjusts the learning parameters and leads the system to converge at the earliest possible time. This technique is appropriate in a sense that optimum learning parameters are being applied in every learning cycle automatically, whereas the conventional backpropagation doesn't contain any well-defined rule regarding the proper determination of the value of learning parameters.

Gradient-based methods for the computation of the velocity from image sequences assume that the velocity field varies smoothly over image. This creates difficulties at regions where the image intensity changes abruptly such as the occluding contours or region boundaries. In this letter, we propose a method to overcome these difficulties by incorporating the information of discontinuities in image intensity into a standard local optimization method. The presented method is applied to the synthetic and real images. The results show that the velocity field computed by the proposed method is less blurred at region boundaries than that of the standard method.

Hot carrier reliability due to residual damage in the gate oxide created by synchrotron X-ray irradiation is investigated for subquarter-micrometer NMOSFETs under a wide irradiation-dose range (103,000 mJ/cm2). Although irradiation-induced interface-traps and positive charges are completely eliminated after 400 post-metalization-annealing, neutral electron traps partially remain. The effects of the residual trapa on hot-carrier degradation can be negligible when gate oxides thinner than about 5 nm are used, and it is found that there is no effect of irradiation damage on interface-trap generation due to injected hot-carriers. It is concluded that the influence of synchrotron radiation X-ray lithography on hot-carrier-induced degradation in subquarter-micrometer NMOSFETs can be negligible.

In formulating the motion constraint equation, we implicitly take it for granted that the spatial and temporal sampling intervals are very small. In real situations, since the intervals cannot be considered sufficiently small, an error will be introduced into the constraint equation and consequently the velocity estimate will be subject to an error due to inaccuracy of the constraint equation. We perform some experiments to analyze the effect of sampling interval on motion estimation. The understanding of experimental results will provide an insight into necessity and amount of image filtering prior to the application of motion estimation.

This paper describes operating characteristics of a new device named multi-step function MOS transistor (MSF MOSFET) which has stair-shaped I-V curve caused by a stairshaped gap between drain and gate. A quantizing inverter is obtained by using only a single MSF MOSFET as a coupling element of an emitter common amplifier. A pair of the quantizing inverters whose input and output are cross-coupled to each other has multi-stable states. This multiple-valued (MV) flip-flop is available for MV registers and MV memories whose states are changeable by an analog input voltage.

This paper presents a design of a new multiple-valued matching VLSI processor for high-speed reasoning. It is useful in the application for real-time rule-based systems with large knowledge bases which are programmable. In order to realize high-speed reasoning, the matching VLSI processor can perform the fully parallel pattern matching between an input data and rules. On the based of direct multiple-valued encoding of each attribute in an input data and rules, pattern matching can be described by using only a programmable delta literal. Moreover, the programmable delta literal circuit can be easily implemented using two kinds of floating-gate MOS devices whose threshold voltages are controllable. In fact, it is demonstrated that four kinds of threshold voltages in a practical floating-gate MOS device can be easily programmable by appropriately controlling the gate, the drain and the source voltage. Finally, the inference time of the quaternary matching VLSI processor with 256 rules and conflict resolution circuits is estimated at about 360 (ns), and the chip area is reduced to about 30 percent, in comparison with the equivalent binary implementation.

A discrete-time neuron model having a refractory period and containing a binary hysteresis output function is introduced. A detailed mathematical analysis of the output response is carried out and the necessary and sufficient condition which a sequence must satisfy in order to be designated as a periodic response of the neuron model under a constant or periodic stimulation is given.

In this paper, a methodology for designing the architecture of the processor array for wide class of image processing algorithms is proposed. A concept of spatially expanding the SFG description which enables us to handle the problem as merely one-dimensional signal processing is used in constructing the methodology. Problem of I/O interface which is critical in real-time processing is also considered.

This paper proposes an ATM traffic management method that utilizes a deterministic source traffic descriptor, a deterministic Usage Parameter Control (UPC) algorithm and a conservative statistical bandwidth allocation method all of which were developed considering the Cell Delay Variation (CDV) typically experienced in ATM networks. For the source traffic descriptor, sliding time interval-type descriptors are proposed. A newly-structured UPC method which combines a sliding window-type circuit and a 2-phase credit window type circuit is proposed. The method is precise and accurate and requires only a small amount of hardware. The proposed parameter conversion method considers the CDV generated between User and UPC point. A bandwidth allocation method based on the worst clumping pattern and UPC output pattern is proposed. The network efficiency degradation caused by CDV is calculated. This traffic management method not only guarantees the QOS of all connections but also allows for large statistical multiplexing gains. The proposed method will, therefore, make it possible to create a more effective B-ISDN, one that can offer cost-effective broadband VBR services.

An accurate numerical solution is presented for the electromagnetic scattering from a double strip grating, where the strip planes are each supported by a dielectric slab. This structure is a model of polarization diplexers. The direction of propagation and the polarization of the incident plane wave are arbitrary. We derive a set of singular integral equations and solve it by the moment method, where the Chebyshev polynomials are successfully used as the basis and the testing functions. By numerical computations we examine the dependence of the diplexing properties on grating parameters in detail. The cross-polarization characteristics at skew incidence are also referred. From these results we construct an algorithm for the design of polarization diplexers.

We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits 1, 0, 1), and their implementation in a 64-bit RISC microprocessor. The multiplier uses a redundant binary adaptation of the Booth algorithm and a redundant binary adder tree. We compared it to a multiplier using a two bit version of the Booth algorithm and a Wallace tree and found that the former multiplier is useful in VLSI because of its high-speed operation, small number of transistors, and good regularity. We also found that the divider performed by Newton's iteration using the multiplier is useful in VLSI. Implementing the multiplier and divider in a highly integrated 64-bit RISC microprocessor, we obtained a high-speed microprocessor.

Although the perception of gloss is based on human visual perception, some methods for measuring glossiness, in contrast to human ability, have been proposed involving plane surfaces. Glossiness defined in these methods, however, does not correspond with psychological glossiness perceived by the human eye over the wide range from relatively low gloss to high gloss. In addition, the change in the incident angle causes a deviation in the measurement of glossiness. A new method for measuring glossiness is proposed in this study. For the new definition of glossiness Gd, the brightness function is utilized. We also extract the value of smoothness of the object's surfaces for use as a factor of glossiness. The measuring equipment consists of a light source, an optical system and a personal computer. Glossiness Gd of paper and plastics is measured with the use of this equipment. In all samples, a strong correlation, with a correlation coefficient of more than 0.97, has been observed between Gd and psychological glossiness Gph. The variance of measured glossiness due to the change in the incident angle of light is small in comparison with that of conventional methods. Based on these findings, it has been found that this method is useful for measuring glossiness of plane objects in the range from relatively low gloss to high gloss.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 3232 bit multiplier reduces the number of active elements to two-third and the number of interconnections to one-fifth of the corresponding binary Wallace tree multiplier, where the speed is almost the same. The structure is simple and regular. The static power dissipation of the designed 32-bit multiplier is estimated to be the mean value of 212 mW and the worst case of 708 mW. The total power including dynamic power dissipation would not be so large compared with that of the 32-bit binary CMOS multiplier reported under 10 MHz operation.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.