In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.

Stochastic Petri Nets and Generalized Stochastic Petri Nets as well as other extensions to Stochastic Petri Nets have been widely applied as a model of asynchronous concurrent process, or as an aid to analyze or design concurrent systems. This paper presents an Extended Stochastic Petri Net model for a shift processing system in which three kinds of sink may occur and an arbitrary time distribution is incorporated, provides an analytical method based on a Markov renewal process with some non-regeneration points to clarify the probabilistic behavior of the system, and finally evaluates the performance of the system with numerical values.

This paper presents the EXM-algorithm, which locates multiple logic design errors in a combinational circuit with multiple output. The error possibility index and the six-valued simulation method have been enhanced to be applied to multiple output circuit. The algorithm locates multiple errors even if they belong to different cone circuits, and processes faster than the conventional EX-algorithm for circuits with the similar gate sizes. Experimental results have shown that the algorithm locates all errors at high hit ratio for ISCAS benchmark circuits and some other circuits.

The pursuit of higher availability has resulted in the development of fault tolerant systems for many industries. However, system characteristics that can be perceived by the customer have never been diagnosed quantitatively. This paper considers the application of stochastic Petri nets with general firing times to modeling of a fault tolerant system and the use of discrete-event simulation methods for stochastic Petri nets to study the behavior of the system. The stochastic Petri net model incorporates factors that compose the system as well as those that accompany it, including RAS characteristics of products, personnel arrangements, and system management. By modeling the behavioral aspect of each factor, it is possible to diagnose a fault tolerant system quantitatively on the basis of customer impact.

The subject of the paper is the minimum initial marking problem for scheduling in timed Petri net PN: given a vector X of nonnegative integers, a P-invariant Y of PN and a nonnegative integer π, find an initial marking M minimizing the value YtrM among those initial marking M such that there is a scheduling σ having the total completion time τ(σ)π with respect M , X and PN (a sequence of transitions, with the first transition firable on M , such that every transition t can fire prescribed number X(t) of times). The paper shows NP-hardness of the problem and proposes two approximation algorithms with their experimental evaluation.

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (dm), the maximum delay time (dM), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between dm and dM. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.

Recent trends in down-sizing have resulted in the development of client server systems for many industries. This paper considers the application of stochastic Petri nets with general firing times for modeling of a concatenated client server system and the use of discrete-event simulation methods for stochastic Petri nets to study its behavior. This approach enables us to assess the most appropriate resource set of a concatenated client server system on the quantitative basis of the performability and the occurrence of system down conditions. Thus, system consultation, a new application of stochastic Petri nets, is presented.

This paper describes MENDELS ZONE, a Petri-net-based concurrent programming environment, which is especially suitable for cooperating discrete event systems. MENDELS ZONE adopts MENDEL net, which is a type of high level (hierarchical colored) Petri net. One of the characteristics of the MENDEL nets is a process-oriented hierarchy like CCS, which is different from the subnet-oriented hierarchy in the Jensen's hierarchical colored Petri net. In a process-oriented hierarchy, a hierarchical unit is a process, which is more natural for cooperating and decentralized discrete event control systems. This paper also proposes a design methodology for MENDEL nets. Although many Petri net tools have been proposed, most tools support only drawing, simulation, and analysis of Petri nets; few tools support the design methodology for Petri nets. While Petri nets are good final design documents easy to understand, analyzable, and executable it is often difficult to write Petri nets directly in an earlier design phase when the system structure is obscure. A proposed design methodology makes a designer to construct MENDEL nets systematically using causality matrices and temporal logic. Furthemore, constructed MENDEL nets can be automatically compiled into a concurrent programming language and executed on a parallel computer.

This paper describes a programming system, K-NET for the development of control software for flexible manufacturing systems composed of robots, numerically-controlled machines, transfer machines and automatic storage/retrieval systems. K-NET is based on a high-level Petri net which makes it simple to express operational functions such as synchronization, interlock and concurrence in sequence control. Petri net in K-NET is colored one in which tokens have attributes, and timed one which can provide a notion of stochastic time. K-NET provides many kinds of boxes having specific functions, and gates specified the firing condition and the token flow control with IF-THEN rules. On the other hand, procedural language can be also used for information processing. K-NET can support all development stages including general design, detailed design, programming and testing. K-NET has an editor to input control specifications expressed with Petri net; a simulator to verify edited specifications; a generator to convert the net to C source programs for a computer or to ladder diagrams for a programmable controller; a reporter to print control specifications; and a monitor to display controller status in real-time. K-NET has been used in the development of control software for an automated guided vehicle system, and results show a 2/3rds cost-saving over development with conventional methods in which only procedural language is used.

This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.

The paper describes a novel 32-bit RISC microprocessor architecture for embedded systems. Variable-length instructions of 16, 32 or 48 bits provide compact code since the majority of instructions are 16 bits in length. The basic instruction format of 16 bits allows only 2 register adresses of 5 bits each; however, it is shown that the overhead in the instruction count is only between 14% and is far outweighed by the savings in program size. The register set provides addressing of 16 global and up to max. 16 local registers per stack frame in a register stack of 64 registers. The stack frames are of variable length with a variable overlap for parameter passing. A load/store architecture is used; memory accesses are pipelined. Nearly all instructions execute in a single cycle. A two-stage pipeline (decode/execute) minimizes wait cycles after pipeline breaks due to branches. An instruction cache of 128 bytes employs an efficient look-ahead algorithm and is quickly updated in case of a cache miss. The µP is implemented in 1.2 µm CMOS on a die of 47 mm2. Power dissipation is only 0.5 W. The development environment is PC-based.

This paper describes a modeling of the cryptography based on a concept of Petri nets. Movement of tokens in the net model shows a dynamic behavior of systems. On the other hand, the cryptography is considered as a bit operation, so that we can point out a common property between the net structure and the cryptography, which provides our idea that movement of tokens of the net model corresponds to a bitoperation of the cryptography. Some effective keys in the net model are considered by means of the net elements, which are based on T-invariant and net structures. It is shown that the keys of the net structured cryptography provide reasonable strength comparing with the data encryption standard (DES).

An effective bitline technique for high density DRAMs is studies. The open-type bitline structure where the bitlines are activated alternately can decrease the bitline noises and the current dissipation in memory cell arrays. In spite of several disadvantages inherent to the open-type bitline structure, this technique is found to get the larger read-out signal than the conventional bitline configurations for the DRAMs of 64 Mb and beyond. The effectiveness is confirmed with the measurement of the test-chips. This technique is expected to be more efficient for DRAMs of higher density, where the contribution of the inter-bitline capacitance is increased.

This paper presents a protocol verification method which verifies that the behaviors of a protocol meet requirements. In this method, a protocol specification is expressed as Extended Finite State Machines (EFSM's) that can handle variables, and requirements are expressed using a branching-time temporal logic for a concise and unambiguous description. Using the acyclic expansion algorithm extended such that it can deal with EFSM's, the verification method first generates a state transition graph consisting of executable transitions for each process. Then a branching-time temporal logic formula representing a requirement is evaluated on one of the generated graphs which is relevant to the requirement. An executable state transition graph for each process is much smaller than a global state transition graph which has been used in the conventional verification techniques to represent the behaviors of the whole protocol system consisting of all processes. The computation for generating the graphs is also reduced to much extent for a large complex protocol. As a result, the presented method achieves efficient verification for requirements regarding a state of a process, transmission and reception of messages by a process, varibales of a process and sequences that interact among processes. The validity of the method is illustrated in the paper by the verification of a path-updating protocol for requirements such as process state reachability or fair termination among processes.

We have successfully developed an optical receiver and a laser driver circuit which were implemented with 0.35 µm GaAs JFETs (junction Field Effect Transistors). The 0.35 µm GaAs. JFET had the typical transconductance of 480 mS/mm with small drain conductance. An interdigit MSM (Metal Semiconductor Metal) -type photodetector and the JFETs were monolithically integrated on a GaAs substrate for the optical receiver. The fabricated optical receiver demonstrated Gb/s operation with a very low power consumption of 8.2 mW. The laser driver circuit operated at up to 4.0 Gb/s.

High frequency and low power 128/129 dual modulus prescaler ICs are developed for mobile communication applications, using 0.5 µm GaAs MESFET technology. Provided with an on-chip voltage regulator, a prescaler IC with an input amplifier operates in a wide frequency range from 200 MHz to 1,500 MHz at input power from -15 dBm to +17 dBm at the temperature of -30 to +120 with supply voltage of 2.7 V, 3.0 V and 5.0 V. At the same time, it demonstrated its low power characteristics consuming 3.68 mA with 3.0 V at +30 in operation, 0.16 mA while powered-off. Another prescaler IC without an input amplifier operates up to 1,650 MHz with Vdd=2.7 V, 3.0 V and 5.0 V at +30, dissipating 2.74 mA/3.0 V.

A job shop system typically seen in flexible manufacturing systems (FMS) is a system composed of a set of machines and a various kind of jobs processed with the machines. A production system of semiconductor fabrication is an example of job shop systems, which has main features of repetitive processes of one part and set-up times required for machines processing different types of parts. On the other hand, timed Petri nets are used for modelling and analyzing a wide variety of discrete event systems. There are many applications of timed Petri nets to the scheduling problems of job shop systems. The performance evaluation and steady state behaviors are studied by using the maximum cycle time of timed marked graphs. The aim of this paper is to propose a new model for production systems including repetitive processes and set-up time requirements which enables the quantitative analysis of real time system performance. In job shop systems such as a semiconductor fabrication system, it takes considerable amount of set-up time to prepare different types of chemical reactions and the model should take account of a set-up time for each machine. We focus upon the relationship between facility utilization factor and production cycle time in the steady state. In the proposed model, the minimum total set-up time can be attained. Quantitative relationship between utilization factor and production cycle time is derived by using the proposed model. A utilization factor of a system satisfying a given limit of the cycle time is evaluated, and the improvement of the utilization factor is considered. Conversely, we consider the improvement of the cycle time of a system satisfying a given limit of utilization factor.

The paper describes the design considerations, fabrication process and performance of the newly developed 1-K ECL gate array implemented with fully self-aligned AlGaAs/GaAs hoterojunction bipolar transistors (HBTs). This gate array consists of 960 three-input OR/NOR ECL basic gates. It contains about 7,600 transistors in a chip area 8.15-mm8.45-mm. The basic (FI=FO=1, wiring length L=0-mm) and loaded (FI=FO=3, L=1-mm) gates exhibit delay times of 33-ps and 82-ps, respectively, with 8.5-mW/gate power dissipation. From the measured values, fan-in, fan-out and wiring delay times of 9-ps/FI, 7-ps/FO and 17-ps/mm are estimated, respectively. These results are in good agreement with the designed results obtained using "SPICE" simulation.

This paper describes the architecture and the performances of a GaAs 88 self-routing switch LSI for ATM switching system. The communication system such as broadband integrated sevices digital network (B-ISDN) requires the hardware switch LSI which exchanges packet cells at a date rate up to several Gb/s. GaAs LSIs are suitable for such application because of its high speed operation and low power dissipation. To clarify the feasibility of GaAs LSI, an 88 self-routing switch LSI is fabricated using 0.5 µm gate GaAs MESFETs and its oerformances are examined. This LSI consists of a switching network for exchanging the packet cells and the "NEMAWASHI" network which detects the cell destined to the same output port. The basic network architecture is a self-routing switch using Batcher-Banyan network. This network consists of basic 22 switch element. Since each element switches the route accorging to the destination of the input cells, self-routing operation is performed without the external circuit for routing control. The LSI is fabricated using 0.5 µm gate GaAs MESFETs. 7003 logic gate are integrated on the chip of 8.2 mm7.4 mm. To reduce the impedance of ground line on the chip and to obtain the enough noise margin, the third level interconnection with low sheet resistance is implemented. As the results of functional evalution, the full function of switching network and "NEMAWASHI" network are verified. Maximum operation speed of 1 GHz is obtained.

This paper describes a VLSI processor architecture designed for a back-propagation accelerator. Three techniques are used to accelerate the simulation. The first is a multi-processor approach where a neural network simulation is suitable for parallel processing. By constructing a ring network using several processors, the simulation speed is multiplied by the number of the processors. The second technique is internal parallel processing. Each processor contains 4 multipliers and 4 ALUs that all work in parallel. The third technique is pipelining. The connections of eight functional units change according to the current stage of the back-propagation algorithm. Intermediate data is sent from one functional unit to another without being stored in extra registers and data is processed in a pipeline manner. The data is in 24-bit floating point format (18-bit mantissa and 6-bit oxponent). The chip has about 88,000 gates, including microcode ROM for processor control, the processor is designed using 0.8-µm CMOS gate arrays, and the estimated performance at 40 MHz is 20 million connection updates per second (MCUPS). For a ring network with 4 processors, performance can be enhanced up to 90 MCUPS.