The paper describes the design considerations, fabrication process and performance of the newly developed 1-K ECL gate array implemented with fully self-aligned AlGaAs/GaAs hoterojunction bipolar transistors (HBTs). This gate array consists of 960 three-input OR/NOR ECL basic gates. It contains about 7,600 transistors in a chip area 8.15-mm8.45-mm. The basic (FI=FO=1, wiring length L=0-mm) and loaded (FI=FO=3, L=1-mm) gates exhibit delay times of 33-ps and 82-ps, respectively, with 8.5-mW/gate power dissipation. From the measured values, fan-in, fan-out and wiring delay times of 9-ps/FI, 7-ps/FO and 17-ps/mm are estimated, respectively. These results are in good agreement with the designed results obtained using "SPICE" simulation.

This paper describes a VLSI processor architecture designed for a back-propagation accelerator. Three techniques are used to accelerate the simulation. The first is a multi-processor approach where a neural network simulation is suitable for parallel processing. By constructing a ring network using several processors, the simulation speed is multiplied by the number of the processors. The second technique is internal parallel processing. Each processor contains 4 multipliers and 4 ALUs that all work in parallel. The third technique is pipelining. The connections of eight functional units change according to the current stage of the back-propagation algorithm. Intermediate data is sent from one functional unit to another without being stored in extra registers and data is processed in a pipeline manner. The data is in 24-bit floating point format (18-bit mantissa and 6-bit oxponent). The chip has about 88,000 gates, including microcode ROM for processor control, the processor is designed using 0.8-µm CMOS gate arrays, and the estimated performance at 40 MHz is 20 million connection updates per second (MCUPS). For a ring network with 4 processors, performance can be enhanced up to 90 MCUPS.

A new algorithm for timing driven placement based on the fuzzy theory is proposed. In this method, the signal delay on the longest path, the chip area and the total wire length can be simultaneously minimized. Introducing the probability measures of fuzzy events, falling down into the local optimal solutions can be avoided. At first, we define the fuzzy placement relation using the graph distance matrix and fuzzy distance relation matrix, and we give a new placement method based on the fuzzy placement relation and the probability measures of fuzzy events. Secondly, we extend this placement method so as to apply to the timing driven placement problem by introducing a fuzzy membership functions which represent the signal delay on the longest path and the chip area. Finally, experimental results are shown to compare our method with one of the previous methods.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

Net-Oriented Analysis and Design (NOAD) is defined as three items: (1) Various nets are utilized as an effective modeling method. (2) Inter-relationships among verious nets are determined. (3) Verification or analysis methods for nets are provided and they are implemented based on the mathematical theory, that is Net theory. Very few methods have been presented to satisfy these three items. For example, the Real-Time SA method covers item (1) only. The Object-Oriented Analysis and Design method (OOA/OOD) covers items (1) and (2). NOAD can be regarded as an extension to OOA/OOD. This paper discusses how effectively various nets have been used in actual software development support metnods and tools and evaluates such several methods and tools from the NOAD viewpoint.

An automatic macrocell generator has been developed and applied to the analog layout of SC and active-RC filters. The generator consists of a process independent generation procedure, a leafcell library, and a circuit description of the leafcells. The unit element arrays of the whole filter are generated together to minimize the array height of the entire filter macrocell, so that the area of the generated filter is as small as that of a manually laid out filter. Three SC filters and one active-RC filter were designed and fabricated by 1.5-µm CMOS technology, that successfully yielded an S/N ratio of more than 70 dB with a quick turn around time.

We propose a hierarchical multi-layer global router for Sea-Of-Gates VLSI's, which is different from the conventional global routers, in that routing and layering are executed simultaneously. The main problems to be solved in the global routing for a multi-layer VLSI are which wire segments are laid out on upper layers and how they are connected to terminals located on lower layers. The main objective is to minimize the maximum of local congestions of all layers. We solve these problems in a hierarchical manner by routing from upper layers to lower layers.

An effective bitline technique for high density DRAMs is studies. The open-type bitline structure where the bitlines are activated alternately can decrease the bitline noises and the current dissipation in memory cell arrays. In spite of several disadvantages inherent to the open-type bitline structure, this technique is found to get the larger read-out signal than the conventional bitline configurations for the DRAMs of 64 Mb and beyond. The effectiveness is confirmed with the measurement of the test-chips. This technique is expected to be more efficient for DRAMs of higher density, where the contribution of the inter-bitline capacitance is increased.

This paper presents an efficient heuristic algorithm for min-cut bisection of weighted hypergraphs. The proposed algorithm is based on a heuristic algorithm proposed by Kahng, which was devised for non-weighted hypergraph bisection, adopting a non-weighted graph called intersection graph to represent a given hypergraph. In the proposed algorithm, instead of an intersection graph, a bipartite graph called netgraph is newly introduced to explicitly represent the weights of nodes of a hypergraph. Using the netgraph, it is easy to partition a weighted hypergraph into two hypergraphs with same size. Computation time of the proposed method is O(m2), where m is the number of nodes of a given hypergraph. Experimental results with real circuit data show that the proposed method produces better solutions in shorter computation time compared with existing methods.

This paper deals with the sub-problems of generating a mask pattern from the logical description of a large-scale CMOS circuit. The large-scale layout can be generated in divide-and-conquer style: divide a given circuit into a set of sub-circuits, generate the layout of each sub-circuit, and merge the resulting layouts to create the whole layout. This paper proposes a layout synthesis algorithm for a sub-circuit with physical constraints for the synthesis scheme above. The physical constraints considered here are the relative placement of logic cells (sets of logic gates) and the routing constraint based on the costs of wiring layers and vias. These constraints will be given by the global optimizer in a two-dimensional layout synthesis routine, and they should be kept at the subsequent one-dimensional layout synthesis for a sub-circuit. The latter is also given for enhancing the circuit performance by limiting the usage of wiring layers and vias for special net such as a clock net. The placement constraint is maintained using PQ-tree, a tree structure representing a set of restricted permutations of elements. One-dimensional layout synthesis determines the placement of transistors by the enhanced pairwise exchanging method under the PQ-tree representation. The routing constraints is considered in the newly developed line-search routing method using a cost-based searching. Experimental results for practical standard cells, including up to 200 transistors, prove that the algorithms can produce the layouts comparable to handcrafted cells. Also on a two-dimensional layout synthesis using the algorithms, the results for benchmark circuits of Physical Design Workshop 1989, i.e., MCNC benchmark circuits, are superior to the best results exhibited at Design Automation Conference 1990.

The subject of the paper is to propose two approximation algorithms FM_SPLA, FM_DPLA for priority-list scheduling in timed Petri nets. Their capability is compared with that of existing algorithms SPLA, DPLA through experimental results, where SPLA and DPLA have previously been proposed by the authors.

Boolean unification is an algorithm to obtain the general solution of a given Boolean equation. Since a general solution provides a way to represent a complete don't care set, Boolean unification can be a powerful technique when applied to logic synthesis. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics of combinational logic synthesis: redesign, multi-level logic minimization and minimization of Boolean relations are discussed. All these problems can be uniformly formalized as Boolean equations. Experimental results are also reported.

This paper proposes a test case generation method for testing concurrent programs as a black box. Typical applications are system testing for switching systems and inter-operability testing for OSI products. We adopt a two-step approach: first generate the control flow graph which represents global behaviors of a given concurrent program, and then apply conventional test case generation methods for the control flow graph. To generate a control flow graph without state space explosion, the black-box equivalence between system behaviors is introduced. The proposed algorithm generates a minimal control flow graph which consists of representatives of equivalence classes. Two practical techniques for the second step are discussed for a case study using a commercial digital PBX. The results show the feasibility of the proposed method.

This paper describes a computer-aided service creation environment (CSCE) for the intelligent network which supports easier graphical specification description for service designers of various skill levels, and service logic program (SLP) generation. The CSCE design concept consists of stepwise service specification description and SLP generation, message sequence chart description language (LSDL: Layered Service Specification Description Language), computer-aided sophisticated interface (IEDs: Intelligent Editors), automatic specification verification and rapid service prototyping. Service specification is described by three steps and in LSDL or SDL, and SLPs are generated through three converters referring to two knowledge databases. Three tests are conducted on the specifications described. The effectiveness of the CSCE is demonstrated by the results that the amount of SLP descriptions for five new practical services using the CSCE is reduced to less than about 20% in LSDL description, compared to C language description.

This paper presents the dynamics of heavy-ion induced latchup turn-on behavior in CMOS structures using a three-dimensional and transient device simulation. The three-dimensional effects of parasitic devices in a CMOS structure during latchup turn-on are discussed in detail when a heavy-ion strikes the CMOS structure. For different incident types, the dynamics of latchup turn-on behaviors are also simulated. Moreover, latchup immunities of the CMOS structure obtained by two- and three-dimensional calculations are compared for the different incident types. This result suggests that the rough relation between latchup immunity and heavy-ion incident energy can be estimated using a two-dimensional simulation.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.

In this paper, the software structure for telecommunication user support are discussed, and it is proposed to apply knowledge processing technology to the software. Capabilities of telecommunications networks are becoming quite complicated, and the number of service items and parameters which have to be selected and memorized will become too large for telecommunications end users to make full use of the network capabilities. As such, more effort should be focused on assisting telecommunications end users to use the network and providing user friendly human interfaces of the network. However, this kind of software has additional type of requirements other than those for protocol handling software and call control software, and the realization of such support software has not yet been fully studied. To realize such support software, this paper stressed the realization of the user-system interface. Especially identified in this paper are meaning-based interpretation of user inputs to permit the handling of synonyms and multivocations, and a method to access the database in the support system without consideration of its data schema. To satisfy these objectives, this paper has proposed that the application data should be represented in both a character string and a meaning representation, and that the thesauruses should have the attribute-value relation. In line with these studies, an experimental system called CAPRIS (CAlling PRocedure Instruction System) was developed. It is used to assist the calling party in a telecommunications network to find an appropriate contact point depending on the purpose of the communication. Implementation of CAPRIS is completed and it was confirmed that all the functions described in this paper were actually realized. Some functional experiments were performed on CAPRIS, and the system was concluded to realize satisfactory user-friendliness.

We developed a 32-bit pseudorandom number generator (RNG) operating at liquid nitrogen temperature based on HEMT ICs. It generates maximum-length-sequence codes whose primitive polynomial is X47+X42+1 with the period of 247-1 clock cycle. We designed and fabricated three kinds of cryogenic HEMT IC for this system: A 1306-gate controller IC, a 3319-gate pseudorandom number generator (RNG) IC, and a buffer IC containing a 4-kb RAM and 514 gates. We used 0.6-µm gate-length Se-doped GaAlAs/GaAs HEMTs. Interconnects were Al for the first layer and Au/Pt/Ti for the second layer with a SiON insulator between them. The HEMT ICs have direct-coupled FET logic (DCFL) gates internally and emitter-coupled logic (ECL) compatible input-putput buffers. The unloaded basic delay of the DCFL gate was 17 ps/gate with a power consumption of 1.4 mW/gate at liquid nitrogen temperature. We used an automatic cryogenic wafer probe we developed and an IC tester for function tests, and used a high-speed performance measuring system we also developed with a bandwidth of more than 20 GHz for high-speed performance tests. Power dissipations were 3.8 W for the controller IC, 4.5 W for the RNG IC, and 3.0 W for the buffer IC. The RNG IC, the largest of the three HEMT ICs, had a maximum operating clock rate of 1.6 GHz at liquid nitrogen temperature. We submerged a specially developed zirconium ceramic printed circuit board carrying the HEMT ICs in a closed-cycle cooling system. The HEMT ICs were flip-chip-packaged on the board with bumps containing indium as the principal component. We confirmed that the RNG system operates at liquid nitrogen temperature and measured a minimum system clock period of 1.49 ns.

An integrated platform INTEGRAL has been developed for developing large complex communication software systems. At the heart of INTEGRAL, a pair of graphical and textual specification languages, DISCOL (DIStributed Communication-Oriented Language), has been developed based on Petri nets. Around DISCOL, a wide variety of design and analysis tools have been integrated in coherent manner so that a seamless support from design to verification and testing are made available along with software life-cycle. The platform has been applied to the development of a PBX simulator named UICPBX. In the development, some real communication services have been fully specified with DISCOL. Such experiences have revealed the effectiveness of the proposed techniques.