A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.

SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.

The intelligent network services will considerably increase the amount of Control and OAM (Operation, Administration and Maintenance) Information (Ic&o) which will be stored in a huge number of distributed databases. Therefore, the management and the organization of databases have become critical issues for securing network performance. This paper studies one of the IN applications that is likely to be an important user of the Ic&o network, namely the Universal Personal Telecommunication (UPT). UPT enables the personal mobility, based on a UPT number related to the user and not a terminal equipment. The Ic&o information of UPT is carried through an ATM based transport network. Taking two fundamental parameters into consideration, namely delay time and the number of users, and two kinds of data location probabilities, this paper studies two basic procedures for finding target data in UPT databases, i.e., chaining and broadcasting. Results show that, when the data location probability is uniform, the broad-casting mode is the faster mode but, on the other hand, the chaining mode allows a larger number of users because the disk access time is less restrictive than in the broadcasting mode. Moreover, this study shows that increasing the number of databases also increases the allowed number of users up to a specific threshold. With a Broadcast Chaining mode, a better compromise between the delay time and the number of allowed users is obtained. If the probability depends on the location of databases (the probability is conversely proportional to the square of the number of searched databases), the results show that the chaining mode is preferable from both the number of users allowed and the delay time viewpoints. Finally, the implementation aspect is discussed.

The static characteristics of GaInAs(P)/GaInAsP quantum well laser diodes (QW LDs), with graded-index separate-confinement-heterostructure (GRIN-SCH) grown by metalorganic chemical vapor deposition (MOCVD), have been investigated experimentally in terms of threshold current density, internal waveguide loss, differential quantum efficiency and light output power. Very low threshold current density of 410 A/cm2, high characteristic temperature of 113 K, low internal waveguide loss of 5 cm-1, high differential quantum efficiency of 82% and high light output power of 100 mW were obtained in 1.3 µm GRIN-SCH multiple quantum well (MQW) LDs by optimizing the quantum well structure including confinement layer and cavity design. Excellent uniformity for the threshold current, quantum efficiency and emission wavelength was obtained in all MOCVD grown buried heterostructure GRIN-SCH MQW LDs. Lasing characteristics of 1.5 µm GRIN-SCH MQW LDs are also described.

This paper describes high-temperature operation of nMOSFET on bonded SOI. A long-channel nMOSFET is fabricated on bonded SOI (Si layer thickness 0.3 µm), SOS (Si layer thickness 0.3 µm), and bulk Si, Bonded SOI is produced using pulse-field-assisited bonding and resistivity-sensitive etching. The high-temperature operation of bonded SOI nMOSFET is demonstrated and compared with SOS and bulk MOSFETs. The leakage current variation with temperature is signnificantly smaller in bonded SOI and in SOS than in bulk MOSFETs. At high temperatures, the drain current to leakage current ratio is 100 times higher in bonded SOI than in SOS and bulk devices. At 300, a ratio of 104 is obtained for the bonded SOI nMOSFET. The ratio is expected to be even higher if a reduced channel length and ultrathin (less than 0.1 µm) bonded SOI is used.

Localized temperature distribution in silicon on insulator (SOI) structures with trench isolations is calculated using three-dimensional computer simulation. Temperature rise in SOI transistors is about three times higher than in conventional structure transistors because the thermal conductivity of SiO2 is very low. If there are voids in the SiO2 layers and trench isolations, temperature in the SOI transistors increases significantly. A simple model is proposed to calculate steady-state temperature rise in SOI transistors.

The interface between laser-recrystallized Si and SiO2 is investigated by means of capacitance-voltage curve measurements. The recrystallization is performed by scanning cw Ar+ laser. The change in the C-V curves shows that the laser-recrystallization generates positive charge and the fast interface states at the Si-SiO2 interface, and creates n-type defects in recrystallized bulk silicon. Nominal interface charge increases linearly with a laser power. The increase in the charge is enhanced by fast laser-beam scanning velocity. The change in the C-V curve is suppressed, if a substrate is heated up to 450 during recrystallization. Complete recovery of the induced change in the C-V curves requires a subsequent furnace annealing at a temperature as high as 1100. These phenomena are explained by the generation of oxygen vacancy at the Si-SiO2 interface and quenched-in point defects in the recrystallized Si. The oxygen vacancy is produced by a reaction between the melted Si and SiO2. The quenched-in defects are produced during fast cooling of the melted Si.

Charges in buried oxide layers formed by wafer bonding were evaluated by capacitance-voltage (C-V) measurements. In this study, silicon-insulator-silicon (SIS) and metal-oxide-silicon (MOS) capacitors were fabricated on bonded wafers. For analyzing C-V curves of SIS structures, C-V simulation programs were developed. From the analysis, we conclude that approximately 2 1011/cm2 negative charges were distributed uniformly in the oxide. The effect of the experimental conditions during wafer bonding on generated charges in buried oxides is also discussed.

The threading dislocation density and the structure of SIMOX wafers formed under different implantation conditions have been invenstigated using Secco etching, cross-sectional transmission electron microscopy and Raman spectroscopy. The breakdown voltage of the buried oxide layer has also been studied. The dislocation density is greatly affected by the dose and the wafer temperature during implantation. The SIMOX wafer implanted at 180 keV with a substoichiometric dose of 0.4 1018 O+ cm-2 at 550 and subsequently annealed at 1350 has an extremely low dislocation density on the order of 102 cm-2. The effect of the wafer temperature on the reduction of the dislocation density is discussed.

Dynamic performance of ultra-thin SIMOX (Separation by IMplanted OXgen) CMOS circuits has been studied using ring oscillators. A novel concept of current-delay product, along with an equivalent linear resistance of MOSFETs, is applied for deriving effective load capacitance of near 0.1 µm gate CMOS circuits. Calculation results showed quatitative agreement with measurement data. It was found that the gate-fringing capacitance limits the delay time is the case of under 0.2 µm gate-length. The lower bound of power-delay product of SIMOX/SOI is expected as low as 0.2 fJ for the gate length of 0.15 µm at the supply voltage of 1.5 V.

A detailed numerical solution of the design criteria of in-phase lateral and single-longitudinal-mode operation GaInAsP/InP DFB laser arrays is presented. The analysis, including broad-area pumped and stripe-geometry pumped index-guided arrays, was carried out on the basis of the eigenvalue equation method. It is shown that there exists a cut-off array pitch co, at which all of the higher-order array modes are cut off. For the pitch larger than the cut-off pitch co, the modal discrimination is evaluated by the threshold gain difference between the in-phase lateral and higher-order array modes. As a result, the modal discrimination was found to decrease with the increase of the number of elements and the array pitch which is limited to be smaller than twice the cut-off pitch co to attain a stable in-phase lateral- and single-longitudinal-mode operation.

Frequency Selective Screens (FSS) with conductor or complementary aperture array are investigated. The electric current distribution on conductor or the magnetic current distribution on aperture is determined by the moment method in the spectral domain. In addition, the power reflection coefficients are calculated and the scattering properties are considered.

Chaotic behavior in a series resonance circuit with a ferroelectric triglycine sulfate (TGS) crystal was observed just below the ferroelectric phase transition temperature. We have analyzed the nonlinear responses by applying external electric fields to the crystal. The computer simulation was made for the modified forroelectric hysteresis loops to realize the experimental results. The fractal correlation dimension was determined to be ν=1.8 in the chaotic phase.

This paper surveys the developments and achievements of teletraffic studies in Japan. It briefly covers the period preceding 1970, then focuses on the period after 1970. Rather than attempting to cover the entire field of teletraffic engineering, it places its emphasis on basic models.

A multicast error control protocol proposed by Metzner is generalized and the performance of the proposed protocol on random error channels (binary symmetric channels) is analyzed. The proposed protocol adopts an encoding procedure based on a product code structure, whith enables each destined user terminal to decode the received frames with the Reddy-Robinson algorithm. As a result, the performance degradation due to the re-broadcasting of the replicas of the previously transmitted frames can be circumvented. The numerical results for the analysis and the simulation indicate that the proposed protocol yields higher throughput and less degradation of throughput with an increase of the number of destined terminals.

Separability is a valuable property of nonlinear mappings. By exploiting this property, computational complexity of many numerical algorithms can be substantially reduced. In this letter, a new algorithm is presented that detects the separability of nonlinear mappings using the concept of "computational graph". A hybrid algorithm using both the top-down search and the bottom-up search is proposed. It is shown that this hybrid algorithm is advantageous in detecting the separability of nonlinear simultaneous functions.

We fabricated a 4 GHz thin-base (120 nm) lateral bipolar transistor on bonded SOI by applying our sidewall self-aligning base process. By applying this device to BiCMOS circuits, bipolar transistor base junction capacitance, and MOSFET source and drain capacitance were very small. Furthermore, MOSFET and bipolar transistors are completely isolated from each other. Thus, it is easy to optimize MOS and bipolar processes, and provide protection from latch-up problems and soft errors caused by α-particles. In this paper, we describe device characteristics and discuss the crystal quality degradation introduced by ion implantation, and two dimensional effects of base diffusion capacitance.

The objective of this work is to demonstrate a new hierarchical timing analysis technique for multi-phase clocked designs with feedback loops including level sensitive latches. By using this technique, large synchronous designs can be analyzed accurately without loop breaking.

An adaptive fuzzy network (AFN) is described that can be used to implement most of fuzzy logic functions. We introduce a learning algorithm largely borrowed from backpropagation algorithm and train the AFN system for several typical fuzzy problems. Simulations show that an adaptive fuzzy network can be implemented with the proposed network and algorithm, which would be impractical for a conventional fuzzy system.