Localized temperature distribution in silicon on insulator (SOI) structures with trench isolations is calculated using three-dimensional computer simulation. Temperature rise in SOI transistors is about three times higher than in conventional structure transistors because the thermal conductivity of SiO2 is very low. If there are voids in the SiO2 layers and trench isolations, temperature in the SOI transistors increases significantly. A simple model is proposed to calculate steady-state temperature rise in SOI transistors.

This paper describes high-temperature operation of nMOSFET on bonded SOI. A long-channel nMOSFET is fabricated on bonded SOI (Si layer thickness 0.3 µm), SOS (Si layer thickness 0.3 µm), and bulk Si, Bonded SOI is produced using pulse-field-assisited bonding and resistivity-sensitive etching. The high-temperature operation of bonded SOI nMOSFET is demonstrated and compared with SOS and bulk MOSFETs. The leakage current variation with temperature is signnificantly smaller in bonded SOI and in SOS than in bulk MOSFETs. At high temperatures, the drain current to leakage current ratio is 100 times higher in bonded SOI than in SOS and bulk devices. At 300, a ratio of 104 is obtained for the bonded SOI nMOSFET. The ratio is expected to be even higher if a reduced channel length and ultrathin (less than 0.1 µm) bonded SOI is used.

A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.

The static characteristics of GaInAs(P)/GaInAsP quantum well laser diodes (QW LDs), with graded-index separate-confinement-heterostructure (GRIN-SCH) grown by metalorganic chemical vapor deposition (MOCVD), have been investigated experimentally in terms of threshold current density, internal waveguide loss, differential quantum efficiency and light output power. Very low threshold current density of 410 A/cm2, high characteristic temperature of 113 K, low internal waveguide loss of 5 cm-1, high differential quantum efficiency of 82% and high light output power of 100 mW were obtained in 1.3 µm GRIN-SCH multiple quantum well (MQW) LDs by optimizing the quantum well structure including confinement layer and cavity design. Excellent uniformity for the threshold current, quantum efficiency and emission wavelength was obtained in all MOCVD grown buried heterostructure GRIN-SCH MQW LDs. Lasing characteristics of 1.5 µm GRIN-SCH MQW LDs are also described.

SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.

Dynamic performance of ultra-thin SIMOX (Separation by IMplanted OXgen) CMOS circuits has been studied using ring oscillators. A novel concept of current-delay product, along with an equivalent linear resistance of MOSFETs, is applied for deriving effective load capacitance of near 0.1 µm gate CMOS circuits. Calculation results showed quatitative agreement with measurement data. It was found that the gate-fringing capacitance limits the delay time is the case of under 0.2 µm gate-length. The lower bound of power-delay product of SIMOX/SOI is expected as low as 0.2 fJ for the gate length of 0.15 µm at the supply voltage of 1.5 V.

We fabricated mixed-signal ICs (MSICs) using wafer-bonded SOI devices with a film several microns thick. We found the MOSFETs on wafer-bonded SOI had characteristics as good as those on a conventional wafer provided the active Si layer is more than 2 µm thick. We fabricated a 16-bit SOI-CMOS delta-sigma A/D converter that suppressed digital noise interference via the substrate. We also fabricated a rectifier-merged SOI-BiCMOS circuit. The resulting characteristics were good, and not possible using conventional junction isolation. Our results suggest that SOI-based isolation is a key technology in integrating devices and systems on a single chip.

The threading dislocation density and the structure of SIMOX wafers formed under different implantation conditions have been invenstigated using Secco etching, cross-sectional transmission electron microscopy and Raman spectroscopy. The breakdown voltage of the buried oxide layer has also been studied. The dislocation density is greatly affected by the dose and the wafer temperature during implantation. The SIMOX wafer implanted at 180 keV with a substoichiometric dose of 0.4 1018 O+ cm-2 at 550 and subsequently annealed at 1350 has an extremely low dislocation density on the order of 102 cm-2. The effect of the wafer temperature on the reduction of the dislocation density is discussed.

The paper deals with the evaluation of channel allotment criteria in a mixed cellular environment composed by a regular grid of macrocells, plus a number of microcells deployed in the most congested areas. The optimum allotment of the resources between microcells and macrocells, which is a key issue for future personal communication systems, has to be tailored on the basis of their different functionalities. The approach is quite innovative since the analysis is carried out considering real traffic statistics, which are characterised by peaks and fluctuations resulting in uneven traffic loads on different cells. Different propagation models for macrocells and microcells have been adopted. Finally, the impact of the allotment of frequency resources to microcells and macrocells is analysed.

One model of a laser is a set of differential equations called the Maxwell-Bloch equations. Actually, in a physical system, causing a chaotic behavior is very difficult. However the chaotic behavior can be observed easily in the system which has a mirror to feedback the delayed output.

Ideal style of arguments of the error function complement contained in the expression for the Norton's surface wave of a vertical dipole over the plane earth is discussed, and then it is pointed out that new formulas have not necessarily desired form as compared with old ones.

In this paper, we propose a new network organizing method for packet radio networks, a layered self-organizing method. In the layered self-organizing network, whole service area is divided into multiple sub-areas and one base station is settled in each sub-area. Communication links are settled in shorter time than the conventional self-organizing method. We evaluate the network organizing performance of the method by using simulations.

This letter describes an MOS operational transconductance amplifier and an MOS four-quadrant analog multiplier using the quadritail cell, which provides an output current proportional to the square of a differential input voltage. As a result, a linear transconductance amplifier and a quarter-squarer multiplier can be obtained in theoretical circuit analysis.

Fahlman and Lebiere's (FL) learning algorithm begins with a two-layer network and in course of training, can construct various network architectures. We applied FL algorithm to the same three-layer network architecture as a back propagation (BP) network and compared their generalization properties. Simulation results show that FL algorithm yields excellent saturation of hidden units which can not be achieved by BP algorithm and furthermore, has more desirable generalization ability than that of BP algorithm.

A divided work-line scheme which uses a bipolar current-switch circuit is proposed. This structures allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-swich circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-µm BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.

The self-checking design using 2-rail logic is one of the most popular design of self-shecking circuits. Even for a self-checking circuit, a test is necessary after VLSI chip or system fabrication, at each time the system is powered, and, under certain circumstances, in the case of maintenance. Therefore, an easy test scheme is desirable for that circuit. A new design method for a 2-rail logic combinational circuit is proposed, where stuck-open and sutck-on faults FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, DOR and DAND, are also added to the circuit as fault observing gates. Each test consists of a sequence of 3 input vectors, that is, a type of 3-pattern test, ti1ti2ti3. A test can be easily generated and fault observation is easy. Stuck-at fault and stuck-open fault on lines and almost all multiple faults can also be detected by the test. A gate construction method, test generation method, circuit construction method, and several discussions including gate delay increasing are presented.

When a group of developers are involved in the distributed development of some software product, they must communicate with one another frequently to exchange information about the product. To reduce the penalty of communication, the support environment should provide developers with their necessary information and update the information automatically while the product is modified by developers. Furthermore, the environment must meet the following requirements despite of workstation failures: whether a specific information is correct or not should always be decidable; as much information as possible should be updated correctly and efficiently. This paper presents a framework to construct such a fault-tolerant environment based on attribute grammars. In the framework, a product is represented by an attributed tree, which is partitioned into several subtrees {T1,,Tm}. Attribute values in each subtree Ti(1im) express the information about the product required by a developer. We introduce a set of redundant data and algorithms to meet the fault-tolerance requirements mentioned above. The correctness of an attribute value in Ti can then be decided in O(mn0log n) time, where n0n, and n is the number of attribute instances in Ti. All available attribute values can be updated with time complexity O(m2n1 log n) and communication complexity O(m2), where n1 is the number of attribute instances that must be reevaluated.

Synchronous clocks are an essential requirement for a variety of distributed system applications. Many of these applications are safety-critical and require fault tolerance. In this paper, a general probabilistic clock synchronization model is presented. This model is uniformly probabilistic, incorporating random message delays, random clock drifts, and random fault occurrences. The model allows faults in any system component and of any type. Also, a new Sliding Window Clock Synchronization Algorithm (SWA) providing increased fault tolerance is proposed. The probabilistic model is used for an evaluation of SWA which shows that SWA is capable of tolerating significantly more faults than other algorithms and that the synchronization tightness is as good or better than that of other algorithms.

Unidirectional/Asymmetric error control codes have extensively been studied, not only from theoretical interest but from application to computer systems or communication systems. Recently, attention has been focused on detecting only d, not all, unidirectional errors, that is, d bits unidirectional error ditecting (d-UED) codes. Borden proposed an optimal nonsystematic d-UED code. This paper shows a new design method for cost-effective self-testing checker for the optimal d-UED code. The checking policy is to check whether condition of the Borden code satisfies or not. The proposed checker includes the parallel weight counter, the comparator and th e modulo adder in which new residue operation is defined and hence this makes the circuit self-testing. These circuits are designed to have all possible input patterns in order to satisfy self-testing property. Finally, the proposed checker has greatly reduced hardware amount compared to the existing one.

If a perspective of the "256M/1G era" were to be made from this present, namely the last stage of the development of 64 M DRAMs, the process technologies will show a variety of progress. Some of them would remain only in the extension of the present ones, but others would show a fundamental change including their technological constitutions. The optical lithography will survive even the "256M/1G era" mainly with the innovations of mask technologies. The etching technologies will remain basically the same as the present ones, but will be much more refined. The studies on plasma/redical related surface reactions, however, will bring a variety of surface treatment technologies of new function. The interconnection technologies will encounter various kinds of difficulties both in materials and in processign, and mechanical processing will become one of ULSI processing technologies. The shallow junction technology will merge with the metallization and epitaxial growth technology. The thin dielectrics will approach a critical situation, and it might enhance the device structural change to three dimensional ones. Corresponding to this, the necessity of "vertical processing" will become larger. The bonding SOI technology might overcome these situations of increasing difficulties. On the other hand, the contamination control will be the base of these technology innovations and improvements, exploring a new technology field in addition to the conventional process technology fields.