Video service is slated to be a major application of emerging high-speed communications networks of the future. In particular, full-motion video is designed to take advantage of the high bandwidths that will become affordably available with the advent of B-ISDN. A salient feature of compressed video sources is that they give rise to autocorrelated traffic streams, which are difficult to model with traditional modeling techniques. In this paper, we describe a new methodology, called TES (Transform-Expand-Sample) , for modeling general autocorrelated time series, and we apply it to traffic modeling of compressed video. The main characteristic of this methodology is that it can model an arbitrary marginal distribution and approximate the autocorrelation structure of an empirical sample such as traffic measurements. Furthermore, the empirical marginal (histogram) and leading autocorrelations are captured simultaneously. Practical TES modeling is computationally intensive and is effectively carried out with software support. A computerized modeling environment, called TEStool, is briefly reviewed. TEStool supports a heuristic search approach for fitting a TES model to empirical time series. Finally, we exemplify our approach by two examples of TES video source models, constructed from empirical codec bitrate measurements: one at the frame level and the other at the group-of-block level. The examples demonstrate the efficacy of the TES modeling methodology and the TEStool modeling environment.

Rate based control is a promising way to achieve an efficient packet transmission especially in high speed packet switching networks where round trip delay is much larger than packet transmission time. Although inappropriate tuning for the parameters, increasing and decreasing factors, of the rate control function causes the performance degradation, most of the previous works so far have not studied the effect of the parameters on the performance. In this paper, we investigate the effect of the rate control parameters on the throughput under the condition that the packet loss probability is kept below a specific value, say 10-6. For this purpose, we build a queueing model and carry out a transient analysis to examine the dynamic behavior of the queue length at an intermediate node in a high speed network suffering from large propagation delay. Numerical examples exploit the optimal value of the parameters when one or two source-destination pairs transmit packets. We also discuss the effect of the propagation delay on the performance. Our model can be applicable to investigate the performance of various kinds of rate-based congestion control when the relation between the congestion measure and the rate control mechanism is given explicitly.

The static characteristics of GaInAs(P)/GaInAsP quantum well laser diodes (QW LDs), with graded-index separate-confinement-heterostructure (GRIN-SCH) grown by metalorganic chemical vapor deposition (MOCVD), have been investigated experimentally in terms of threshold current density, internal waveguide loss, differential quantum efficiency and light output power. Very low threshold current density of 410 A/cm2, high characteristic temperature of 113 K, low internal waveguide loss of 5 cm-1, high differential quantum efficiency of 82% and high light output power of 100 mW were obtained in 1.3 µm GRIN-SCH multiple quantum well (MQW) LDs by optimizing the quantum well structure including confinement layer and cavity design. Excellent uniformity for the threshold current, quantum efficiency and emission wavelength was obtained in all MOCVD grown buried heterostructure GRIN-SCH MQW LDs. Lasing characteristics of 1.5 µm GRIN-SCH MQW LDs are also described.

A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.

An adaptive fuzzy network (AFN) is described that can be used to implement most of fuzzy logic functions. We introduce a learning algorithm largely borrowed from backpropagation algorithm and train the AFN system for several typical fuzzy problems. Simulations show that an adaptive fuzzy network can be implemented with the proposed network and algorithm, which would be impractical for a conventional fuzzy system.

Dynamic performance of ultra-thin SIMOX (Separation by IMplanted OXgen) CMOS circuits has been studied using ring oscillators. A novel concept of current-delay product, along with an equivalent linear resistance of MOSFETs, is applied for deriving effective load capacitance of near 0.1 µm gate CMOS circuits. Calculation results showed quatitative agreement with measurement data. It was found that the gate-fringing capacitance limits the delay time is the case of under 0.2 µm gate-length. The lower bound of power-delay product of SIMOX/SOI is expected as low as 0.2 fJ for the gate length of 0.15 µm at the supply voltage of 1.5 V.

This paper describes high-temperature operation of nMOSFET on bonded SOI. A long-channel nMOSFET is fabricated on bonded SOI (Si layer thickness 0.3 µm), SOS (Si layer thickness 0.3 µm), and bulk Si, Bonded SOI is produced using pulse-field-assisited bonding and resistivity-sensitive etching. The high-temperature operation of bonded SOI nMOSFET is demonstrated and compared with SOS and bulk MOSFETs. The leakage current variation with temperature is signnificantly smaller in bonded SOI and in SOS than in bulk MOSFETs. At high temperatures, the drain current to leakage current ratio is 100 times higher in bonded SOI than in SOS and bulk devices. At 300, a ratio of 104 is obtained for the bonded SOI nMOSFET. The ratio is expected to be even higher if a reduced channel length and ultrathin (less than 0.1 µm) bonded SOI is used.

Localized temperature distribution in silicon on insulator (SOI) structures with trench isolations is calculated using three-dimensional computer simulation. Temperature rise in SOI transistors is about three times higher than in conventional structure transistors because the thermal conductivity of SiO2 is very low. If there are voids in the SiO2 layers and trench isolations, temperature in the SOI transistors increases significantly. A simple model is proposed to calculate steady-state temperature rise in SOI transistors.

The interface between laser-recrystallized Si and SiO2 is investigated by means of capacitance-voltage curve measurements. The recrystallization is performed by scanning cw Ar+ laser. The change in the C-V curves shows that the laser-recrystallization generates positive charge and the fast interface states at the Si-SiO2 interface, and creates n-type defects in recrystallized bulk silicon. Nominal interface charge increases linearly with a laser power. The increase in the charge is enhanced by fast laser-beam scanning velocity. The change in the C-V curve is suppressed, if a substrate is heated up to 450 during recrystallization. Complete recovery of the induced change in the C-V curves requires a subsequent furnace annealing at a temperature as high as 1100. These phenomena are explained by the generation of oxygen vacancy at the Si-SiO2 interface and quenched-in point defects in the recrystallized Si. The oxygen vacancy is produced by a reaction between the melted Si and SiO2. The quenched-in defects are produced during fast cooling of the melted Si.

Charges in buried oxide layers formed by wafer bonding were evaluated by capacitance-voltage (C-V) measurements. In this study, silicon-insulator-silicon (SIS) and metal-oxide-silicon (MOS) capacitors were fabricated on bonded wafers. For analyzing C-V curves of SIS structures, C-V simulation programs were developed. From the analysis, we conclude that approximately 2 1011/cm2 negative charges were distributed uniformly in the oxide. The effect of the experimental conditions during wafer bonding on generated charges in buried oxides is also discussed.

The threading dislocation density and the structure of SIMOX wafers formed under different implantation conditions have been invenstigated using Secco etching, cross-sectional transmission electron microscopy and Raman spectroscopy. The breakdown voltage of the buried oxide layer has also been studied. The dislocation density is greatly affected by the dose and the wafer temperature during implantation. The SIMOX wafer implanted at 180 keV with a substoichiometric dose of 0.4 1018 O+ cm-2 at 550 and subsequently annealed at 1350 has an extremely low dislocation density on the order of 102 cm-2. The effect of the wafer temperature on the reduction of the dislocation density is discussed.

We fabricated mixed-signal ICs (MSICs) using wafer-bonded SOI devices with a film several microns thick. We found the MOSFETs on wafer-bonded SOI had characteristics as good as those on a conventional wafer provided the active Si layer is more than 2 µm thick. We fabricated a 16-bit SOI-CMOS delta-sigma A/D converter that suppressed digital noise interference via the substrate. We also fabricated a rectifier-merged SOI-BiCMOS circuit. The resulting characteristics were good, and not possible using conventional junction isolation. Our results suggest that SOI-based isolation is a key technology in integrating devices and systems on a single chip.

We fabricated a 4 GHz thin-base (120 nm) lateral bipolar transistor on bonded SOI by applying our sidewall self-aligning base process. By applying this device to BiCMOS circuits, bipolar transistor base junction capacitance, and MOSFET source and drain capacitance were very small. Furthermore, MOSFET and bipolar transistors are completely isolated from each other. Thus, it is easy to optimize MOS and bipolar processes, and provide protection from latch-up problems and soft errors caused by α-particles. In this paper, we describe device characteristics and discuss the crystal quality degradation introduced by ion implantation, and two dimensional effects of base diffusion capacitance.

This paper is a study on the behavioral aspects of the input buffer limiting scheme whose basic feature is to award priority to the transit messages over the input messages so that congestion does not develop in the network. The numerical method employed in the analysis is that proposed in Ref.(7). The performance aspects are studied for different buffer capacities, different message handling capacities and different levels of reservation for transit traffic. The numerical method indicates that thrashing occurs at low levels of reservation for the transit messages, irrespective of the buffer size or the processor capacities of the node. This observation is supported by simulation results. With reference to the state-space of the model of our study, the congestion aspects are related to two Liapunov functions. Under the domain of one of the Liapunov functions, the evolution of the perturbed system is towards a congested state whereas, under the domain of the other Liapunov function, the evolution is towards a congestion-free state. Regardless of the configuration, it is found that the fundamental characteristic of the congestion under the input buffer limiting scheme is the characteristic of a fold catastrophe. In the systems with insufficient level of reservation for the transit traffic, the performance degradation appears to be inevitable, irrespective of the capacities of the nodal processor and output channel processor, and the size of the buffer pool. Given such an inevitability, the active life of a node under a typical node configuration is studied by simulation. A suitable performance index is suggested to assess the performance of deadlock-prone nodes.

Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 1016 cm-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.

This is a partly expository paper discussing how point processes with certain "bursty" features can be qualitatively modelled by the Markovian arrival process, a generalization of the Poisson or Bernoulli processes which can be used to obtain algorithmically tractable matrix solutions to a variety of problems in probability models.

This letter describes an MOS operational transconductance amplifier and an MOS four-quadrant analog multiplier using the quadritail cell, which provides an output current proportional to the square of a differential input voltage. As a result, a linear transconductance amplifier and a quarter-squarer multiplier can be obtained in theoretical circuit analysis.

Hot-carrier characteristics in ultra-thin SOI MOSFET's (T-SOI MOSFET's) with gate-overlapped LDD have been investigated. The change in transistor static characteristics after hot carrier stress was mainly observed as positive threshold voltage (Vt) shifts due to trapped electrons, while in bulk-Si MOSFET's drain current degradation was dominant. The hot-carrier life time in T-SOI MOSFET's was comparable to that in bulk-Si devices at low drain voltage, but the life time dependence on drain voltage was different from that in bulk-Si MOSFET's, and the Vt degraded rapidly at the condition that parasitic bipolar breakdown began to occur. This implies that the drain supply voltage in T-SOI MOSFET's is determined directly by parasitic bipolar breakdown voltage unlike bulk-Si MOSFET's in which it is determined by hot-carrier reliability. The gate-overlapped LDD structure was compared with single drain structure and proved to provide better hot-carrier endurance by the improvement of the parasitic bipolar breakdown voltage. The hot-carrier reliability in the back channels of T-SOI MOSFET's was also investigated, and it was found that the back channel tends to be degraded more easily than front channel with large positive Vt shifts. These results suggest that the front Vt shifts in T-SOI devices are related with electron injection into the back surface of the T-SOI layer through charge coupling at the condition that the parasitic bipolar breakdown occurs.

A vertex-capacitated network is a graph whose edges and vertices have infinite positive capacities and finite positive capacities, respectively. Such a network is a model of a communication system in which capacities of links are much larger than those of stations. This paper considers a problem of realizing a flow-saturation in an undirected vertex-capacitated network by adding the least number of edges. By defining a set of influenced vertex pairs by adding edges, we show the follwing results.(1) It suffices to add the least number of edges to unsaturated vertex pairs for realizing flow-saturation.(2) An associated graph of a flow-unsaturated network defined in this paper gives us a sufficient condition that flow-saturation is realized by adding a single edge.

Extended interpolatory approximations are discussed for some classes of n-dimensional stochastic signals expressed as the orthogonal expansions with respect to a given set of orthonormal functions. We assume that the norm of the weighted mutual correlation function of the signal is smaller than a given positive number. The presented approximation has the minimum measure of approximation error among all the linear and nonlinear statistical approximations using the similar measure of error and the same generalized moments of these signals.