Eisuke KUDOH Tadashi MATSUMOTO
User capacity of a DS/CDMA cellular mobile radio system employing transmitter power control (TPC) is investigated. Assuming log-normally distributed control error, outage probability is evaluated through computer simulations. The user capacity is dramatically decreased as the power control error increases. If the standard deviation is larger than about 2dB, the user capacity is decreased by more than 60%. It is shown that power control error with a standard deviation of less than or equal to 0.5dB is required to accommodate 90% of the maximum user capacity. The capacity decrease in the reverse and forward link channels due to non-uniform user distributions are also investigated. It is shown that if system users are densely distributed within the zone fringe whose thickness is 80% of the radius, the reverse link capacity is decreased by about 22%. The forward link capacity is comparatively insenstitive to non-uniform user distribution.
Tadashi TAKAGI Kiyoharu SEINO Takuo KASHIWA Tsutomu HASHIMOTO Fumio TAKEDA
A Ka-band 0.5 W monolithic amplifier using a novel tandem FET has been developed. The tandem FET consists of two FET cells connected in series through a short transmission line. The features of the tandem FET are high gain, flat gain response and miniaturized size. The tandem FET is very useful for obtaining high gain, high power amplifiers operating in millimeter-wave region where combining and matching circuits' losses are significantly large. By combining four tandem FETs, a linear gain of 4.5 dB, a 1 dB compressed power of 26.3 dBm and a saturated output power of 27.3 dBm (0.54 W) have been achieved at 37 GHz. The size of the amplifier is 1.73.20.03t mm.
Ikko HARADA Fumio UENO Takahiro INOUE Ichirou OOTA
For a realization of a DC-DC converter using no magnetic devices, a new switched capacitor (SC) transformer is introduced, which gives voltage ratios by Fibonacci series corresponding to the stages. This transformer is connected in cascade by each basic block which is assembled by a capacitor and three MOSFET switches. This operates on a simple two-phase clock and has a large step-up or step-down voltage ratio in spite of its simple configuration. The characteristics of this transformer with n stages of basic block are derived and calculated by means of a 4 4 cascade matrix. The optimal arrangement of each stage's capacitances is shown to reduce the SC resistance by about 20%. The simulation results are compared with the characteristics of a prototype transformer with four stages (8 times step-up ratio). Its power efficiency achieves 88% in case of 97 V output voltage, 0.2 A output current, and 100 kHz switching frequency. Lastly, the proposed SC transformer is compared and discussed with other typical SC transformers.
Yohtaro UMEDA Takatomo ENOKI Kunihiro ARAI Yasunobu ISHII
Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n+-InGaAs/n+-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.
An extremely accurate and very wide-band quadrature modulator IC fabricated on a single chip using bipolar technology is presented. The characteristics of this quadrature modulator IC are much superior to conventional ones (modulation phase error and deviation from quadrature is about 1/10), and this IC is applicable to high modulation schemes such as 256 QAM. In this circuit, the phase difference between local signals input to each of two balanced modulators is detected by a phase detector, and a variable phase shifter in the local port is controlled automatically by the detected signals. This, along with the use of a wide-band variable phase shifter, enables the phase difference between the local signals input to the balanced modulators to be adaptively controlled to 90 degrees in wide frequency bands. In addition, a design method for the balanced modulators to obtain small modulation phase error is described. Based on this design method, a highly accurate quadrature modulator IC was fabricated, in which two balanced modulators, the phase detector, and the variable phase shifter were integrated on a single chip. Phase deviation from quadrature in the local signals was reduced to less than 0.3 degrees in the wide frequency bands of more tham 60 MHz. The modulation phase error of the balanced modulators wes less than 0.2 degrees at 140 MHz, and less than 2.5 degrees at up to 1.3 GHz.
Yasutaka ICHIHASHI Yoshio NAGAKI Takeshi TSUKAMOTO Youichi TAMURA
A method for sweeping frequency ranges of over 130GHz within a tuning range of 30nm, without mode hopping, has been realized. The optical frequency is swept with a fine translation-rotation grating drive which uses a new, simplified operation method and a thermally controlled semiconductor laser system.
Okihiko ISHIZUKA Zheng TANG Akihiro TAKEI Hiroki MATSUMOTO
This paper extends an earlier study on the T-Model neural network to its collective computational properties. We present arguments that it is necessary to use the half-interconnected T-Model networks rather than the fully-interconnected Hopfield model networks. The T-Model has been generated in response to a number of observed weaknesses in the Hopfield model. This paper identities these problems and show how the T-Model overcomes them. The T-Model network is essentially a feedforward network which does not produce a local minimum for computations. A concept for understanding the dynamics of the T-Model neural circuit is presented and its performance is also compared with the Hopfield model. The T-Model neural circuit is implemented and tested with standard CMOS technology. Simulations and experiments show that the T-Model allows immense collective network computations and does not produce a local minimum. High densities comparable to that of the Hopfield model implementations have also been achieved.
Tsuneo TOKUMITSU Takahiro HIRAOKA Hiroyuki NAKAMOTO Masayoshi AIKAWA
Novel, very small-size multilayer MMIC's using miniature microstrip lines on a thin dielectric film, as well as the features of the multilayer structure, are presented. Very narrow-width thin-film transmission lines, meander-like configurations, line crossovers, and vertical connections, which are effective for significant chip-size reduction and flexible layout, are realized and utilized in a 2.5-3 µmN-layer dielectric film structure. 180-degree and 90-degree hybrids and umltiport Wilkinson dividers, which are implemented in small areas of 0.1 mm2 and 1.7 mm2, are presented. Furthermore, layout flexibility in the multilayer structure is demonstrated by implementing distributed amplifiers into the layers.
This paper describes the waveform relaxation (WR) algorithm with the under relaxation method based on the virtual state formulation (VSF) technique and the effect of multirate behavior in this algorithm. First, we present the virtual state relaxation method using VSF technique. Next, we introduce the VSF method into WR algorithm in order to exploit the multirate behavior. Furthermore, we construct the relaxation-based circuit simulator DESIRE2 and apply this simulator to the transient analysis of MOS circuits. Finally, we show that the present technique enables to use efficiently the multirate integration method in VSR and reduce the total simulation time without losing the waveform accuracy.
This paper proposes three configurations of slow-wave transmission lines for MMICs, i.e., double crosstie slow-wave transmission line (DCT-SLW), meander-like DCT-SLW and lumped DCT-SLW. The DCT-SLW is based on periodic structures and triplate structures. The meander-like DCT-SLW realizes a drastic size reduction in the DCT-SLW using a meander configuration of inductive and capacitive transmission lines. The multilayer spiral inductors are introduced to obtain high impedance characteristics of the meander section. The lumped DCT-SLW achieves a large slow-wave factor of 30. These proposed structures are analytically and experimentally investigated, and excellent performance is obtained. It is also shown that the proposed DCT-SLWs are superior to thin film microstrip (TFMS) lines with the same insertion phase, as regards size.
Tomoaki OHTSUKI Hiroyuki YASHIMA Iwao SASASE Shinsaku MORI
We propose the coherent subcarrier multiplexed (SCM) system with distributing local oscillator (LO) in local loop. The proposed system can realize multichannel transmission with one optical carrier by using the SCM technique and has no need to have LO at each station. Therefore the proposed system becomes cost-effective. The proposed SCM system uses bandpass filter to select a specific channel. We analyze CNR of the system with frequency-shift keying (FSK) in a multioctave configuration. First, the general expression of CNR is derived and is shown for the following parameters such as the number of channels, the position of station on the loop, and the number of stations on the loop. Second, optimal phase modulation (PM) index is derived, and the optimal CNR, minimum required power of lasers, and maximum number of stations that the proposed system can serve are shown by using it. Moreover CNR of the proposed system is compared with that of the system having LO at each station in local loop. It is shown that the proposed system can obtain good performance at the expense of slight increase of the output power of only two lasers at the central station. Therefore the proposed system is cost-effective and practical.
The selection method of the moment of inertia of the flywheel in a digital measurement system of torque-speed curve plotting for a kind of motor is presented. The selection standards of the moment of inertia and the map displaying the operating ranges of the measurement system are shown. The selection procedure of the moment of inertia is also shown.
Mamoru SASAKI Nobuyuki ISHIKAWA Fumio UENO Takahiro INOUE
In this paper, voltage-input current-output Membership Function Circuit (MFC) and Normalization Locked Loop (NLL) are proposed. They are useful building blocks for the current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of one source coupled type Operational Transconductance Amplifier (OTA). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. Here, the NLL circuit, which can process the weighted average operation without the divider, is implemented using one source coupled type OTA. The proposed circuits were designed by using 2 µm CMOS design rules and its operations were confirmed using SPICE simulations.
Fumihiko ITO Ken-ichi KITAYAMA
Fourier holographic image storage and reconstruction using BaTiO3 photorefractive crystal waveguide is investigated. The phase conjugation technique, which compensates image distortion caused by modal phase dispersion, successfully retores images stored in a test BaTiO3 crystal waveguide.
Nobuyuki HAYAMA Jun-ichi SHIMIZU Kazuhiko HONJO
Design consideration, fabrication process, and performance of a fully monolithic 22 GHz-band oscillator implemented using a self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) are described. For optimization of the oscillator circuit parameters, large-signal circuit model parameters extracted from bias dependent small-signal S-parameters have been used to maximumize an output power. The developed oscillator employs a 1.510 µm2 emitter AlGaAs/GaAs HBT fabricated by using a dual sidewall self-aligned process. The fabricated oscillator has exhibited an output power of 6.2 dBm at 22.16 GHz with a collector efficiency of 9.5%, and phase noise of 78 dBc/Hz at 100 kHz off-carrier under free-running condition. These results were in good agreement with the large-signal designed results obtained using harmonic balance simulator.
It is difficult for a receiver in Asynchronous SSMA systems to eliminate co-channel interference, when the receiver doesn't know the sequence of the co-channel interference. In this paper, a filter for eliminating co-channel interference without using the knowledge of the sequence of co-channel interference in an asynchronous SSMA system, in which each transmitter/receiver is assigned an infinite number of sequences and select a sequence secretly for information security. The filter gathers the co-channel interference energy into some puleses and scatters the signal energy widely. The receiver can clip the co-channel interference energy by losing small amount of signal energy. This is a new solution for the near-far problem in an asynchronous SSMA system using secret sequences.
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI
This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.
This paper proposes an MMIC image rejection mixer and an MMIC balanced mixer employing multilayer microstrip lines and high-electron-mobility-field-effect-transistor (HEMT)s with a LUFET configuration (line-unified HEMT module). The advantage of the mixers is remarkable chip size reduction by the combination of the two technologies. The multilayer microstrip line, in which one microstrip line is placed upon another, is used for stacking passive circuits, e.g. a 90 hybrid and distributed lines, to reduce the chip-area occupied by transmission lines, and to allow flexible line allocation. The line-unified HEMT module provides all functions required for in-phase/out-of-phase power divider/combiners in HEMT electrode and unified coplanar lines configuration. A 29-32 GHz image rejection mixer and a 3-27 GHz balanced mixer are realized in only 1.6 mm 1.0 mm and 1.8 mm 1.2 mm MMIC chip size, respectively.