In multi user multiple input multiple output systems, spatial precoding is typically employed as an interference cancellation technique. This technique, however, requires accurate channel state information at the transmitter and limits the mobility of the mobile station (MS). Instead of spatial precoding, this letter implements collaborative interference cancellation (CIC) for interference suppression. In CIC, neighboring MSs share their received signals without decoding and equivalently increase the number of received antennas. The performance is evaluated through a field experiment using a vehicle that is equipped with seven MSs and moves around an urban area.

Single-instruction multiple-data (SIMD) extension provides an energy-efficient platform to scale the performance of media and scientific applications while still retaining post-programmability. However, the major challenge is to translate the parallel resources of the SIMD hardware into real application performance. Currently, all the slots in the vector register are used when compilers exploit SIMD parallelism of programs, which can be called sufficient vectorization. Sufficient vectorization means all the data in the vector register is valid. Because all the slots which vector register provides must be used, the chances of vectorizing programs with low SIMD parallelism are abandoned by sufficient vectorization method. In addition, the speedup obtained by full use of vector register sometimes is not as great as that obtained by partial use. Specifically, the length of vector register provided by SIMD extension becomes longer, sufficient vectorization method cannot exploit the SIMD parallelism of programs completely. Therefore, insufficient vectorization method is proposed, which refer to partial use of vector register. First, the adaptation scene of insufficient vectorization is analyzed. Second, the methods of computing inter-iteration and intra-iteration SIMD parallelism for loops are put forward. Furthermore, according to the relationship between the parallelism and vector factor a method is established to make the choice of vectorization method, in order to vectorize programs as well as possible. Finally, code generation strategy for insufficient vectorization is presented. Benchmark test results show that insufficient vectorization method vectorized more programs than sufficient vectorization method by 107.5% and the performance achieved by insufficient vectorization method is 12.1% higher than that achieved by sufficient vectorization method.

In this paper, we present several cryptanalyses of Hierocrypt-L1 block cipher, which was selected as one of the CRYPTREC recommended ciphers in Japan in 2003. We present a differential attack and an impossible differential attack on 8 S-function layers in a related-key setting. We first show that there exist the key scheduling differential characteristics which always hold, then we search for differential paths for the data randomizing part with the minimum active S-boxes using the above key differentials. We also show that our impossible differential attack is a new type.

The RC4 stream cipher is widely used including WEP and WPA, which are the security protocols for IEEE 802.11 wireless standard. WPA improved a construction of the RC4 key setting known as TKIP to avoid the known WEP attacks. The first 3-byte RC4 keys generated by IV in WPA are known since IV can be obtained by observing packets. The weaknesses in TKIP using the known IV were reported by Sen Gupta et al. at FSE 2014 and by Ito and Miyaji at FSE 2015. Both showed that TKIP induces many RC4 key correlations including the keystream bytes or the unknown internal states. Ideally TKIP should be constructed in such a way that it can keep the security level of generic RC4. In the first part of this paper, we will provide newly theoretical proofs of 17 correlations remain unproven in our previous work theoretically. Our theoretical analysis can make clear how TKIP induces biases of internal states in generic RC4. In the second part of this paper, we will further provide a refined construction of the RC4 key setting. As a result, we can reduce the number of correlations in the refined construction by about 70% in comparison with that in the original setting.

This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption/decryption in a single clock cycle. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low-latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.

We propose a framework to perform auto-radiometric calibration in photometric stereo methods to estimate surface orientations of an object from a sequence of images taken using a radiometrically uncalibrated camera under varying illumination conditions. Our proposed framework allows the simultaneous estimation of surface normals and radiometric responses, and as a result can avoid cumbersome and time-consuming radiometric calibration. The key idea of our framework is to use the consistency between the irradiance values converted from pixel values by using the inverse response function and those computed from the surface normals. Consequently, a linear optimization problem is formulated to estimate the surface normals and the response function simultaneously. Finally, experiments on both synthetic and real images demonstrate that our framework enables photometric stereo methods to accurately estimate surface normals even when the images are captured using cameras with unknown and nonlinear response functions.

In this letter, based on cyclic difference sets with parameters $(N,rac{N-1}{2},rac{N-3}{4})$ and complex transformations, a method for constructing degree-4 perfect Gaussian integer sequences (PGISs) with good balance property of length $N'equiv2( ext{mod}4)$ are presented. Furthermore, the elements distribution of the proposed Gaussian integer sequences (GISs) is derived.

In this study, we consider techniques to search for high-rate punctured convolutional code (PCC) encoders using dual code encoders. A low-rate R=1/n convolutional code (CC) has a dual code that is identical to a PCC with rate R=(n-1)/n. This implies that a rate R=1/n convolutional code encoder can assist in searches for high-rate PCC encoders. On the other hand, we can derive a rate R=1/n CC encoder from good PCC encoders with rate R=(n-1)/n using dual code encoders. This paper proposes a method to obtain improved high-rate PCC encoders, using exhaustive search results of PCC encoders with rate R=1/3 original encoders, and dual code encoders. We also show some PCC encoders obtained by searches that utilized our method.

An information flow problem is a graph-theoretical formalization of the transportation of information over a complicated network. It is known that a linear network code plays an essential role in a certain type of information flow problems, but it is not understood clearly how contributing linear network codes are for other types of information flow problems. One basic problem concerning this aspect is the linear solvability of information flow problems, which is to decide if there is a linear network code that is a solution to the given information flow problem. Lehman et al. characterize the linear solvability of information flow problems in terms of constraints on the sets of source and sink nodes. As an extension of Lehman's investigation, this study introduces a hierarchy constraint of messages, and discusses the computational complexity of the linear solvability of information flow problems with the hierarchy constraints. Nine classes of problems are newly defined, and classified to one of three categories that were discovered by Lehman et al.

This paper proposes an effective signal processing scheme using a modulation code with two-dimensional (2D) run-length limited (RLL) constraints for bit-patterned media magnetic recording (BPMR). This 2D signal processing scheme is applied to be one of two-dimensional magnetic recording (TDMR) schemes for shingled magnetic recording on bit patterned media (BPM). A TDMR scheme has been pointed out an important key technology for increasing areal density toward 10Tb/in2. From the viewpoint of 2D signal processing for TDMR, multi-track joint decoding scheme is desirable to increase an effective transfer rate because this scheme gets readback signals from several adjacent parallel tracks and detect recorded data written in these tracks simultaneously. Actually, the proposed signal processing scheme for BPMR gets mixed readback signal sequences from the parallel tracks using a single reading head and these readback signal sequences are equalized to a frequency response given by a desired 2D generalized partial response system. In the decoding process, it leads to an increase in the effective transfer rate by using a single maximum likelihood (ML) sequence detector because the recorded data on the parallel tracks are decoded for each time slot. Furthermore, a new joint pattern-dependent noise-predictive (PDNP) sequence detection scheme is investigated for multi-track recording with media noise. This joint PDNP detection is embed in a ML detector and can be useful to eliminate media noise. Using computer simulation, it is shown that the joint PDNP detection scheme is able to compensate media noise in the equalizer output which is correlated and data-dependent.

In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.

Self-updating encryption (SUE) is a new cryptographic scheme produced in the recent work of Lee, Choi, Lee, Park and Yung (Asiacrypt 2013) to achieve a time-updating mechanism for revocation. In SUE, a ciphetext and a private key are associated with the time and a user can decrypt a ciphertext only if its time is earlier than that of his private key. But one drawback is the encryption computational overhead scales with the size of the time which makes it a possible bottleneck for some applications. To address this problem, we provide a new technique for the SUE that splits the encryption algorithm into two phases: an offline phase and an online phase. In the offline phase, an intermediate ciphertext header is generated before it knows the concrete encryption time. Then an online phase is implemented to rapidly generate an SUE ciphertext header when the time becomes known by making use of the intermediate ciphertext header. In addition, two different online encryption constructions are proposed in view of different time level taking 50% as the boundary. At last, we prove the security of our scheme and provide the performance analysis which shows that the vast majority of computational overhead can be moved to the offline phase. One motivating application for this technique is resource-constrained mobile devices: the preparation work can be done when the mobile devices are plugged into a power source, then they can later rapidly perform SUE operations on the move without significantly consuming the battery.

The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking by using Inductive coupling ThruChip Interface (TCI). In order to connect a large number of small chips for building a large scale system, novel chip stacking methods called the linear stacking and staggered stacking are proposed. They enable the system to be extended to x or/and y dimensions, not only to z dimension. Here, a novel chip staking layout, and its deadlock-free routing design for the case using single-core chips and multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 5.4% on average compared to that of 2D mesh.

This paper proposes a multiway power divider for wideband (4:1) beamforming arrays. The divider's input reflection characteristic (S11) is achieved using a multisection stepped-impedance transformer. Moreover, the divider's isolation (S32) bandwidth is increased by incorporating inductors and capacitors in addition to the conventional resistor only isolation networks of the divider. The analysis of the proposed divider and comparison with the previous research model was conducted with four-way configuration. A prototype of a wideband eight-way power divider is fabricated and measured. The measured fractional bandwidth is about 137% from 1.3 to 6.8GHz with the -10dB criteria of input reflection (S11), output reflection (S22) and isolation (S32) simultaneously.

In this paper, we identify the tradeoff between security and reliability in the amplify-and-forward (AF) distributed beamforming (DBF) cooperative network with K untrusted relays. In particular, we derive the closed-form expressions for the connection outage probability (COP), the secrecy outage probability (SOP), the tradeoff relationship, and the secrecy throughput. Analytical and simulation results demonstrate that increasing K leads to the enhancement of the reliability performance, but the degradation of the security performance. This tradeoff also means that there exists an optimal K maximizing the secrecy throughput.

We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm2 active area.

This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.