The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] (42807hit)

9941-9960hit(42807hit)

  • Accurate Image Separation Method for Two Closely Spaced Pedestrians Using UWB Doppler Imaging Radar and Supervised Learning

    Kenshi SAHO  Hiroaki HOMMA  Takuya SAKAMOTO  Toru SATO  Kenichi INOUE  Takeshi FUKUDA  

     
    PAPER-Sensing

      Vol:
    E97-B No:6
      Page(s):
    1223-1233

    Recent studies have focused on developing security systems using micro-Doppler radars to detect human bodies. However, the resolution of these conventional methods is unsuitable for identifying bodies and moreover, most of these conventional methods were designed for a solitary or sufficiently well-spaced targets. This paper proposes a solution to these problems with an image separation method for two closely spaced pedestrian targets. The proposed method first develops an image of the targets using ultra-wide-band (UWB) Doppler imaging radar. Next, the targets in the image are separated using a supervised learning-based separation method trained on a data set extracted using a range profile. We experimentally evaluated the performance of the image separation using some representative supervised separation methods and selected the most appropriate method. Finally, we reject false points caused by target interference based on the separation result. The experiment, assuming two pedestrians with a body separation of 0.44m, shows that our method accurately separates their images using a UWB Doppler radar with a nominal down-range resolution of 0.3m. We describe applications using various target positions, establish the performance, and derive optimal settings for our method.

  • Quantizer Design Optimized for Distributed Estimation

    Yoon Hak KIM  

     
    LETTER-Fundamentals of Information Systems

      Vol:
    E97-D No:6
      Page(s):
    1639-1643

    We consider the problem of optimizing the quantizer design for distributed estimation systems where all nodes located at different sites collect measurements and transmit quantized data to a fusion node, which then produces an estimate of the parameter of interest. For this problem, the goal is to minimize the amount of information that the nodes have to transmit in order to attain a certain application accuracy. We propose an iterative quantizer design algorithm that seeks to find a non-regular mapping between quantization partitions and their codewords so as to minimize global distortion such as the estimation error. We apply the proposed algorithm to a system where an acoustic amplitude sensor model is employed at each node for source localization. Our experiments demonstrate that a significant performance gain can be achieved by our technique as compared with standard typical designs and even with distributed novel designs recently published.

  • Bimodal Vertex Splitting: Acceleration of Quadtree Triangulation for Terrain Rendering

    Eun-Seok LEE  Jin-Hee LEE  Byeong-Seok SHIN  

     
    PAPER-Computer Graphics

      Vol:
    E97-D No:6
      Page(s):
    1624-1633

    Massive digital elevation models require a large number of geometric primitives that exceed the throughput of the existing graphics hardware. For the interactive visualization of these datasets, several adaptive reconstruction methods that reduce the number of primitives have been introduced over the decades. Quadtree triangulation, based on subdivision of the terrain into rectangular patches at different resolutions, is the most frequently used terrain reconstruction method. This usually accomplishes the triangulation using LOD (level-of-detail) selection and crack removal based on geometric errors. In this paper, we present bimodal vertex splitting, which performs LOD selection and crack removal concurrently on a GPU. The first mode splits each vertex for LOD selection and the second splits each vertex for crack removal. By performing these two operations concurrently on a GPU, we can efficiently accelerate the rendering speed by reducing the computation time and amount of transmission data in comparison with existing quadtree-based rendering methods.

  • Accurate Height Change Estimation Method Using Phase Interferometry of Multiple Band-Divided SAR Images

    Ryo NAKAMATA  Ryo OYAMA  Shouhei KIDERA  Tetsuo KIRIMOTO  

     
    PAPER-Sensing

      Vol:
    E97-B No:6
      Page(s):
    1205-1214

    Synthetic aperture radar (SAR) is an indispensable tool for low visibility ground surface measurement owing to its robustness against optically harsh environments such as adverse weather or darkness. As a leading-edge approach for SAR image processing, the coherent change detection (CCD) technique has been recently established; it detects a temporal change in the same region according to the phase interferometry of two complex SAR images. However, in the case of general damage assessment following an earthquake or mudslide, the technique requires not only the detection of surface change but also an assessment for height change quantity, such as occurs with a building collapse or road subsidence. While the interferometric SAR (InSAR) approach is suitable for height assessment, it is basically unable to detect change if only a single observation is made. To address this issue, we previously proposed a method of estimating height change according to phase interferometry of the coherence function obtained by dual band-divided SAR images. However, the accuracy of this method significantly degrades in noisy situations owing to the use of the phase difference. To resolve this problem, this paper proposes a novel height estimation method by exploiting the frequency characteristic of coherence phases obtained by each SAR image multiply band-divided. The results obtained from numerical simulations and experimental data demonstrate that our proposed method offers accurate height change estimation while avoiding degradation in the spatial resolution.

  • Throughput and Power Efficiency Evaluation of Block Ciphers on Kepler and GCN GPUs Using Micro-Benchmark Analysis

    Naoki NISHIKAWA  Keisuke IWAI  Hidema TANAKA  Takakazu KUROKAWA  

     
    PAPER-Fundamentals of Information Systems

      Vol:
    E97-D No:6
      Page(s):
    1506-1515

    Computer systems with GPUs are expected to become a strong methodology for high-speed encryption processing. Moreover, power consumption has remained a primary deterrent for such processing on devices of all sizes. However, GPU vendors are currently announcing their future roadmaps of GPU architecture development: Nvidia Corp. promotes the Kepler architecture and AMD Corp. emphasizes the GCN architecture. Therefore, we evaluated throughput and power efficiency of three 128-bit block ciphers on GPUs with recent Nvidia Kepler and AMD GCN architectures. From our experiments, whereas the throughput and per-watt throughput of AES-128 on Radeon HD 7970 (2048 cores) with GCN architecture are 205.0Gbps and 1.3Gbps/Watt respectively, those on Geforce GTX 680 (1536 cores) with Kepler architecture are, respectively, 63.9Gbps and 0.43Gbps/W; an approximately 3.2 times throughput difference occurs between AES-128 on the two GPUs. Next, we investigate the reasons for the throughput difference using our micro-benchmark suites. According to the results, we speculate that to ameliorate Kepler GPUs as co-processor of block ciphers, the arithmetic and logical instructions must be improved in terms of software and hardware.

  • Analysis of Lower Bounds for the Multislope Ski-Rental Problem

    Hiroshi FUJIWARA  Yasuhiro KONNO  Toshihiro FUJITO  

     
    PAPER

      Vol:
    E97-A No:6
      Page(s):
    1200-1205

    The multislope ski-rental problem is an extension of the classical ski-rental problem, where the player has several options of paying both of a per-time fee and an initial fee, in addition to pure renting and buying options. Damaschke gave a lower bound of 3.62 on the competitive ratio for the case where arbitrary number of options can be offered. In this paper we propose a scheme that for the number of options given as an input, provides a lower bound on the competitive ratio, by extending the method of Damaschke. This is the first to establish a lower bound for each of the 5-or-more-option cases, for example, a lower bound of 2.95 for the 5-option case, 3.08 for the 6-option case, and 3.18 for the 7-option case. Moreover, it turns out that our lower bounds for the 3- and 4-option cases respectively coincide with the known upper bounds. We therefore conjecture that our scheme in general derives a matching lower and upper bound.

  • The Design of Low Complexity S-Boxes Based on a Discretized Piecewise Linear Chaotic Map

    Daisaburo YOSHIOKA  Akio TSUNEDA  

     
    PAPER-Nonlinear Problems

      Vol:
    E97-A No:6
      Page(s):
    1396-1404

    Since substitution boxes (S-boxes) are the only nonlinear portion of most block ciphers, the design of cryptographically strong and low-complexity S-boxes is of great importance in cryptosystems. In this paper, a new kind of S-boxes obtained by iterating a discretized piecewise linear map is proposed. The S-box has an implementation efficiency both in software and hardware. Moreover, the results of performance test show that the proposed S-box has good cryptographic properties.

  • High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

    Naoya ONIZAWA  Akira MOCHIZUKI  Hirokatsu SHIRAHAMA  Masashi IMAI  Tomohiro YONEDA  Takahiro HANYU  

     
    PAPER-Dependable Computing

      Vol:
    E97-D No:6
      Page(s):
    1546-1556

    This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).

  • A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS

    Sho IKEDA  Sangyeop LEE  Tatsuya KAMIMURA  Hiroyuki ITO  Noboru ISHIHARA  Kazuya MASU  

     
    PAPER

      Vol:
    E97-C No:6
      Page(s):
    495-504

    This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

  • FOREWORD Open Access

    Akira HYOGO  

     
    FOREWORD

      Vol:
    E97-C No:6
      Page(s):
    468-468
  • FOREWORD

    Kazuyuki AMANO  

     
    FOREWORD

      Vol:
    E97-A No:6
      Page(s):
    1162-1162
  • Introduction of Yield Quadrant and Yield Capability Index for VLSI Manufacturing

    Junichi HIRASE  

     
    PAPER-Semiconductor Materials and Devices

      Vol:
    E97-C No:6
      Page(s):
    609-618

    Yield enhancements and quality improvements must be considered as factors of the utmost importance in VLSI (Very Large Scale Integration circuits) manufacturing in order to reduce cost and ensure customer satisfaction. This paper will present a study of the yield theory, an analysis of actual manufacturing data, and the challenges of yield enhancement.

  • Fingerprint Verification and Identification Based on Local Geometric Invariants Constructed from Minutiae Points and Augmented with Global Directional Filterbank Features

    Chuchart PINTAVIROOJ  Fernand S. COHEN  Woranut IAMPA  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E97-D No:6
      Page(s):
    1599-1613

    This paper addresses the problems of fingerprint identification and verification when a query fingerprint is taken under conditions that differ from those under which the fingerprint of the same person stored in a database was constructed. This occurs when using a different fingerprint scanner with a different pressure, resulting in a fingerprint impression that is smeared and distorted in accordance with a geometric transformation (e.g., affine or even non-linear). Minutiae points on a query fingerprint are matched and aligned to those on one of the fingerprints in the database, using a set of absolute invariants constructed from the shape and/or size of minutiae triangles depending on the assumed map. Once the best candidate match is declared and the corresponding minutiae points are flagged, the query fingerprint image is warped against the candidate fingerprint image in accordance with the estimated warping map. An identification/verification cost function using a combination of distance map and global directional filterbank (DFB) features is then utilized to verify and identify a query fingerprint against candidate fingerprint(s). Performance of the algorithm yields an area of 0.99967 (perfect classification is a value of 1) under the receiver operating characteristic (ROC) curve based on a database consisting of a total of 1680 fingerprint images captured from 240 fingers. The average probability of error was found to be 0.713%. Our algorithm also yields the smallest false non-match rate (FNMR) for a comparable false match rate (FMR) when compared to the well-known technique of DFB features and triangulation-based matching integrated with modeling non-linear deformation. This work represents an advance in resolving the fingerprint identification problem beyond the state-of-the-art approaches in both performance and robustness.

  • Image Retargeting with Protection of Object Arrangement

    Kazu MISHIBA  Takeshi YOSHITOME  

     
    PAPER-Image Processing and Video Processing

      Vol:
    E97-D No:6
      Page(s):
    1583-1589

    The relative arrangement, such as relative positions and orientations among objects, can play an important role in expressing the situation such as sports games and race scenes. In this paper, we propose a retargeting method that allows maintaining the relative arrangement. Our proposed retargeting method is based on a warping method which finds an optimal transformation by solving an energy minimization problem. To achieve protection of object arrangement, we introduce an energy that enforces all the objects and the relative positions among these objects to be transformed by the same transformation in the retargeting process. In addition, our method imposes the following three types of conditions in order to obtain more satisfactory results: protection of important regions, avoiding extreme deformation, and cropping with preservation of the balance of visual importance. Experimental results demonstrate that our proposed method maintains the relative arrangement while protecting important regions.

  • Illumination Normalization-Based Face Detection under Varying Illumination

    Min YAO  Hiroshi NAGAHASHI  Kota AOKI  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E97-D No:6
      Page(s):
    1590-1598

    A number of well-known learning-based face detectors can achieve extraordinary performance in controlled environments. But face detection under varying illumination is still challenging. Possible solutions to this illumination problem could be creating illumination invariant features or utilizing skin color information. However, the features and skin colors are not sufficiently reliable under difficult lighting conditions. Another possible solution is to do illumination normalization (e.g., Histogram Equalization (HE)) prior to executing face detectors. However, applications of normalization to face detection have not been widely studied in the literature. This paper applies and evaluates various existing normalization methods under the framework of combining the illumination normalization and two learning-based face detectors (Haar-like face detector and LBP face detector). These methods were initially proposed for different purposes (face recognition or image quality enhancement), but some of them significantly improve the original face detectors and lead to better performance than HE according to the results of the comparative experiments on two databases. Meanwhile, we propose a new normalization method called segmentation-based half histogram stretching and truncation (SH) for face detection under varying illumination. It first employs Otsu method to segment the histogram (intensities) of the input image into several spans and then does the redistribution on the segmented spans. In this way, the non-uniform illumination can be efficiently compensated and local facial structures can be appropriately enhanced. Our method obtains good performance according to the experiments.

  • Utilizing Global Syntactic Tree Features for Phrase Reordering

    Yeon-Soo LEE  Hyoung-Gyu LEE  Hae-Chang RIM  Young-Sook HWANG  

     
    LETTER-Natural Language Processing

      Vol:
    E97-D No:6
      Page(s):
    1694-1698

    In phrase-based statistical machine translation, long distance reordering problem is one of the most challenging issues when translating syntactically distant language pairs. In this paper, we propose a novel reordering model to solve this problem. In our model, reordering is affected by the overall structures of sentences such as listings, reduplications, and modifications as well as the relationships of adjacent phrases. To this end, we reflect global syntactic contexts including the parts that are not yet translated during the decoding process.

  • Design of Small CRPA Arrays for Dual-Band GPS Applications

    Gangil BYUN  Seung Mo SEO  Ikmo PARK  Hosung CHOO  

     
    PAPER-Antennas and Propagation

      Vol:
    E97-B No:6
      Page(s):
    1130-1138

    This paper proposes the design of small CRPA arrays for dual-band Global Positioning System (GPS) applications. The array consists of five elements and is mounted on a circular ground platform with a diameter of 15-cm. Each antenna element has a coupled feed structure and consists of a feed patch and two radiating patches for dual-band operation. An external chip coupler is utilized for a broad circular polarization (CP) bandwidth, and its measured characteristics are taken into account in our simulation for more accurate performance estimation. Detailed parameters are optimized by using a genetic algorithm (GA) in conjunction with the FEKO EM simulator. The optimized antenna is fabricated on a ceramic substrate, and its performance is measured in a full anechoic chamber. Furthermore, a field test is also conducted to verify the signal-to-noise ratio (SNR) for real GPS satellite signals. The results prove that the proposed array is suitable for use in GPS CRPA applications.

  • Implicit Generation of Pattern-Avoiding Permutations by Using Permutation Decision Diagrams

    Yuma INOUE  Takahisa TODA  Shin-ichi MINATO  

     
    PAPER

      Vol:
    E97-A No:6
      Page(s):
    1171-1179

    Pattern-avoiding permutations are permutations where none of the subsequences matches the relative order of a given pattern. Pattern-avoiding permutations are related to practical and abstract mathematical problems and can provide simple representations for such problems. For example, some floorplans, which are used for optimizing very-large-scale integration (VLSI) circuit design, can be encoded into pattern-avoiding permutations. The generation of pattern-avoiding permutations is an important topic in efficient VLSI design and mathematical analysis of patten-avoiding permutations. In this paper, we present an algorithm for generating pattern-avoiding permutations, and extend this algorithm beyond classical patterns to generalized patterns with more restrictions. Our approach is based on the data structure πDDs, which can represent a permutation set compactly and has useful set operations. We demonstrate the efficiency of our algorithm by computational experiments.

  • Sparse Binary-to-Ternary Encoding for Holographic Storage

    Seth PHILLIPS  Ivan FAIR  

     
    PAPER

      Vol:
    E97-A No:6
      Page(s):
    1231-1239

    In holographic data storage, information is recorded within the volume of a holographic medium. Typically, the data is presented as an array of pixels with modulation in amplitude and/or phase. In the 4-f orientation, the Fourier domain representation of the data array is produced optically, and this image is recorded. If the Fourier image contains large peaks, the recording material can saturate, which leads to errors in the read-out data array. In this paper, we present a coding process that produces sparse ternary data arrays. Ternary modulation is used because it inherently provides Fourier domain smoothing and allows more data to be stored per array in comparison to binary modulation. Sparse arrays contain fewer on-pixels than dense arrays, and thus contain less power overall, which reduces the severity of peaks in the Fourier domain. The coding process first converts binary data to a sequence of ternary symbols via a high-rate block code, and then uses guided scrambling to produce a set of candidate codewords, from which the most sparse is selected to complete the encoding process. Our analysis of the guided scrambling division and selection processes demonstrates that, with primitive scrambling polynomials, a sparsity greater than 1/3 is guaranteed for all encoded arrays, and that the probability of this worst-case sparsity decreases with increasing block size.

  • #P-hardness of Computing High Order Derivative and Its Logarithm

    Ei ANDO  

     
    LETTER

      Vol:
    E97-A No:6
      Page(s):
    1382-1384

    In this paper, we show a connection between #P and computing the (real) value of the high order derivative at the origin. Consider, as a problem instance, an integer b and a sufficiently often differentiable function F(x) that is given as a string. Then we consider computing the value F(b)(0) of the b-th derivative of F(x) at the origin. By showing a polynomial as an example, we show that we have FP = #P if we can compute log 2F(b)(0) up to certain precision. The previous statement holds even if F(x) is limited to a function that is analytic at any x ∈ R. It implies the hardness of computing the b-th value of a number sequence from the closed form of its generating function.

9941-9960hit(42807hit)