This paper proposes a new approach to defining and expressing algorithms: the notion of task logical algorithms. This notion allows the user to define an algorithm for a task T as a set of agents who can collectively perform T. This notion considerably simplifies the algorithm development process and can be seen as an integration of the sequential pseudocode and logical algorithms. This observation requires some changes to algorithm development process. We propose a two-step approach: the first step is to define an algorithm for a task T via a set of agents that can collectively perform T. The second step is to translate these agents into (higher-order) computability logic.

This paper presents a 120-GHz-band amplifier module with a hermetic sealing structure for a broadband wireless system. The sealing structure for F-band waveguides is a laminate composed of two sealing plates and a spacer. Each sealing plate has a fused glass window and separates inside air from the ambient atmosphere. The design process of the sealing structure is simple and has good simulation fidelity. The hermetic sealing structure designed for an amplifier in a 120-GHz-band wireless link has an insertion loss of less than 1dB and a return loss of more than 15dB in the operating band. We made three kinds of sealed modules to evaluate the sealing function. The modules sealed with this technique meet the hermetic-seal standard in MIL-STD-883F. We then verified that the sealing structure on the sealed modules has a small enough effect for the transmittance of the intrinsic characteristics. In addition, we performed 10-Gbit/s data transmission using a sealed amplifier module with the bit error rate of less than 10-10.

We propose an architecture for offloading processes in applications to support low-performance devices. Almost all applications based on standardized web technologies are compatible with our architecture. We discuss how interfaces should be used properly to offload processes in JavaScript and argue that an interface for offloading should only be used for defining complex processes. We also propose a method for applying our architecture to web applications that use web workers. Our method automatically offloads some worker processes to the cloud. We also compare the processing times achieved with and without our method. Our architecture exhibits good efficacy with regards to the N-Queen problem, although it is influenced by network latency between a device and the cloud.

E-band communication is allocated to the frequency bands of 71-76 and 81-86GHz. Radio-frequency (RF) front-end components for E-band communication have been realized using compound semiconductor technology. To realize a CMOS LNA for E-band communication, we propose a gain-boosted cascode amplifier (GBCA) stage that simultaneously provides high gain and stability. Designing an LNA from scratch requires considerable time because the tuning of matching networks with consideration of the parasitic elements is complicated. In this paper, we model the characteristics of devices including the effects of their parasitic elements. Using these models, an optimizer can estimate the characteristic of a designed LNA precisely without electromagnetic simulations and gives us the design values of an LNA when the layout constraint is ignored. Starting from the values, a four-stage LNA with a GBCA stage is designed very easily even though the layout constraint is considered and fabricated by a 65nm LP CMOS process. The fabricated LNA is measured, and it is confirmed that it achieves 18.5GHz bandwidth and over 24.3dB gain with 50.6mW power consumption. This is the first LNA to achieve a gain bandwidth of over 300GHz in the E-band among the LNAs utilizing any kind of semiconductor technologies. In this paper, we have proved that CMOS technology, which is suitable for baseband and digital circuitry, is applicable to a communication system covering the entire E-band.

One of the technological innovations that has enabled the VLSI semiconductor industry to reduce the transistor size, increase the number of transistors per die, and also follow Moore's law year after year is the fact that an equivalent yield and equivalent testing quality have been ensured for the same die size. This has contributed to reducing the economically optimum production cost (production cost per component) as advocated by Moore. In this paper, we will verify Moore's law using actual values from VLSI manufacturing sites while introducing some of the technical progress that occurred from 1970 to 2010.

Social media such as microblogs have become so pervasive such that it is now possible to use them as sensors for real-world events and memes. While much recent research has focused on developing automatic methods for filtering and summarizing these data streams, we explore a different trend called social curation. In contrast to automatic methods, social curation is characterized as a human-in-the-loop and sometimes crowd-sourced mechanism for exploiting social media as sensors. Although social curation web services like Togetter, Naver Matome and Storify are gaining popularity, little academic research has studied the phenomenon. In this paper, our goal is to investigate the phenomenon and potential of this new field of social curation. First, we perform an in-depth analysis of a large corpus of curated microblog data. We seek to understand why and how people participate in this laborious curation process. We then explore new ways in which information retrieval and machine learning technologies can be used to assist curators. In particular, we propose a novel method based on a learning-to-rank framework that increases the curator's productivity and breadth of perspective by suggesting which novel microblogs should be added to the curated content.

Many studies have reported that the single-event transient (SET) width increases with temperature. However, the mechanism for this temperature dependency is not clear, especially for an N-hit SET. In this study, TCAD simulations are carried out to study the temperature dependence of N-hit SETs in detail. Several possible factors are examined, and the results show that the temperature dependence in bulk devices is due to the decrease in the carrier mobility with temperature in both the struck NMOS and the pull-up PMOS. In contrast, the temperature dependence in SOI devices is due to the decrease in the diffusion constant and carrier lifetime with temperature, which enhances the parasitic bipolar effect.

The transfer of prior knowledge from source domains can improve the performance of learning when the training data in a target domain are insufficient. In this paper we propose a new strategy to transfer deformable part models (DPMs) for object detection, using offline-trained auxiliary DPMs of similar categories as source models to improve the performance of the target object detector. A DPM presents an object by using a root filter and several part filters. We use these filters of the auxiliary DPMs as prior knowledge and adapt the filters to the target object. With a latent transfer learning method, appropriate local features are extracted for the transfer of part filters. Our experiments demonstrate that this strategy can lead to a detector superior to some state-of-the-art methods.

With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model.

The success of any project can be affected by requirements changes. Requirements elicitation is a series of activities of adding, deleting, and modifying requirements. We refer to the completion of requirements elicitation of a software component as requirements maturation. When the requirements of each component have reached the 100% maturation point, no requirement will come to the component. This does not mean that a requirements analyst (RA) will reject the addition of requirements, but simply, that the additional requirements will not come to the project. Our motivation is to provide measurements by which an RA can estimate one of the maturation periods: the early, middle, or late period of the project. We will proceed by introducing the requirements maturation efficiency (RME). The RME of the requirements represents how quickly the requirements of a component reach 100% maturation. Then, we will estimate the requirements maturation period for every component by applying the RME. We assume that the RME is derived from its accessibility from an RA to the requirements source and the stability of the requirements. We model accessibility as the number of information flows from the source of the requirements to the RA, and further, model stability with the requirements maturation index (RMI). According to the multiple regression analysis of a case, we are able to get an equation on RME derived from these two factors with a significant level of 5%. We evaluated the result by comparing it to another case, and then discuss the effectiveness of the measurements.

A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.

In this letter, we exploit a new framework for detecting the non-specific object via combing the top-down and bottom-up cues. Specifically, a novel supervised discriminative dictionaries learning method is proposed to learn the coupled dictionaries for the object and non-object feature spaces in terms of the top-down cue. Different from previous dictionary learning methods, the new data reconstruction residual terms of coupled feature spaces, the sparsity penalty measures on the representations and an inconsistent regularizer for the learned dictionaries are all incorporated in a unitized objective function. Then we derive an iterative algorithm to alternatively optimize all the variables efficiently. Considering the bottom-up cue, the proposed discriminative dictionaries learning is then integrated with an unsupervised dictionary learning to capture the objectness windows in an image. Experimental results show that the non-specific object detection problem can be effectively solved by the proposed dictionary leaning framework and outperforms some established methods.

The delay time component (τs) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (rs), the value of rs is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of τs depends on the current in a way similar to rs. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter rs than a Si MOSFET.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

Information-Based Access Control (IBAC) has been proposed as an improvement to History-Based Access Control (HBAC) model. In modern component-based systems, these access control models verify that all the code responsible for a security-sensitive operation is sufficiently authorized to execute that operation. The HBAC model, although safe, may incorrectly prevent the execution of operations that should be executed. The IBAC has been shown to be more precise than HBAC maintaining its safety level while allowing sufficiently authorized operations to be executed. However the verification problem of IBAC program has not been discussed. This paper presents a formal model for IBAC programs based on extended weighted pushdown systems (EWPDS). The mapping process between the IBAC original semantics and the EWPDS structure is described. Moreover, the verification problem for IBAC programs is discussed and several typical IBAC program examples using our model are implemented.

For the past couple of decades, the usage of the Web as a platform for deploying software products has become incredibly popular. Web applications became more prevalent, as well as more complex. Countless Web applications have already been designed, developed, tested, and deployed on the Internet. However, it is noticeable that many common functionalities are present among these vast number of applications. This paper proposes an approach based on a database containing information from previous test artifacts. The information is used to generate test scenarios for Web applications under test. We have developed a tool based on our proposed approach, with the aim of reducing the effort required from software test engineers and professionals during the test planning and creation stage of software engineering. We evaluated our approach from three viewpoints: comparison between our approach and manual generation, qualitative evaluation by professional software engineers, and comparison between our approach and two open-source tools.

This paper presents an artificial fish swarm algorithm (AFSA) to solve the multicast routing problem, which is abstracted as a Steiner tree problem in graphs. AFSA adopts a 0-1 encoding scheme to represent the artificial fish (AF), which are then subgraphs in the original graph. For evaluating each AF individual, we decode the subgraph into a Steiner tree. Based on the adopted representation of the AF, we design three AF behaviors: randomly moving, preying, and following. These behaviors are organized by a strategy that guides AF individuals to perform certain behaviors according to certain conditions and circumstances. In order to investigate the performance of our algorithm, we implement exhaustive simulation experiments. The results from the experiments indicate that the proposed algorithm outperforms other intelligence algorithms and can obtain the least-cost multicast routing tree in most cases.

This paper describes a simple packet combining scheme with maximum likelihood detection (MLD) for multiple-input multiple-output with orthogonal frequency division multiplexing (MIMO-OFDM) in relay channels to construct reliable wireless links in wireless local area networks (LANs). Our MLD-based approach employs the multiplexed sub-stream signals in different transmit slots. The proposed scheme uses an additional combining process before MLD processing. Moreover, the proposed scheme sets the cyclic shift delay (CSD) operation in the relay terminal. We evaluate the performance of the proposed scheme by the packet error rate (PER) and throughput performance in the decode-and-forward (DF) strategy. First, we show that the proposed scheme offers approximately 4.5dB improvement over the conventional scheme in the received power ratio of the relay terminal to the destination terminal at PER =0.1. Second, the proposed scheme achieves about 1.6 times the throughput of the conventional scheme when the received power ratio of the relay terminal to the destination terminal is 3dB.

Two types of low-coherence millimeter-wave sources for photonic millimeter-wave ellipsometry are compared. A broadband signal (125-GHz bandwidth) or a narrowband one (0.5-GHz bandwidth) is used to measure the complex relative dielectric constants of purified water, and the narrowband signal is revealed to be suitable for accurate measurement.

This paper presents a G-band triple-push voltage controlled oscillator (VCO) operating around 177GHz. The VCO, implemented in a commercial 0.13-µm RFCMOS technology, adopts a triple-push topology that is composed of 3 symmetrically coupled identical Colpitts sub-oscillators. Oscillation frequency can be tuned from 175.9GHz to 178.4GHz with varactor tuning voltage swept from 0 to 1.2V. The calibrated output power ranged from -19.7dBm to -16.6dBm depending on the oscillation frequency. The measured phase noise of the VCO is -80.2dBc/Hz at 1MHz offset. The results clearly demonstrate the possibility of applying triple-push topology for VCOs operating beyond 100GHz, enabling various high frequency applications that require tunable frequency sources.