We propose a theory of general frame multiresolution analysis (GFMRA) which generalizes both the theory of multiresolution analysis based on an affine orthonormal basis and the theory of frame multiresolution analysis based on an affine frame to a general frame. We also discuss the problem of perfectly representing a function by using a wavelet frame which is not limited to being of affine type. We call it a "generalized affine wavelet frame." We then characterize the GFMRA and provide the necessary and sufficient conditions for the existence of a generalized affine wavelet frame.

We propose a new QOS routing algorithm for finding a path that guarantees several quality of service (QOS) parameters requested by users, for ATM networks. It is known that a routing problem is NP-complete, if the number of additive QOS parameters, such as delay and cost, are more than or equal to two. Although a number of heuristic algorithms have been proposed recently to solve this problem, the appropriate choice of routing algorithms is still an open issue. In this paper, we propose a new heuristic routing algorithm, while being compliant with PNNI routing and signaling specification in the ATM Forum. The performance of algorithms is evaluated by simulation with a various network topologies and loading scenarios. This simulation results demonstrate that the proposed scheme improves the performance while reducing computational complexity.

This paper presets a fast computation algorithm for connection admission control for heterogeneous delay sensitive traffic in ATM networks. Cell loss probability is adopted as the measure of quality of service. In our study, cells of each connection are allowed to have two different loss priorities and the aggregate traffic can have more than two. To cope with multiple quality of service requirements, the link capacity is divided into several bands. For simplicity, each traffic source is assumed to alternate between active and idle periods. However, the results can be extended to traffic sources having more than two states. Upper bounds of actual cell loss probabilities are derived based on the bufferless fluidflow model. Numerical results show that the upper bounds are close to the actual cell loss probabilities.

Nonuniform traffic can degrade the overall performance of multistage interconnection networks substantially. In this paper, this performance degradation is traced back to blocking effects that are not present under uniform traffic patterns within a network. This blocking phenomenon is not mentioned in the literature and is termed higher order Head-of-Line-blocking (HOLk-blocking) in this paper. Methods to determine the HOL-blocking order of multistage networks in order to classify the networks are presented. The performance of networks under hot-spot traffic as a function of their HOL-blocking characteristics is studied by simulation. It is shown that network bandwidth and packet delay improve under nonuniform traffics with increasing HOL-blocking order of a network.

Various reconfiguration schemes against faults of mesh-connected processor arrays have been proposed. As one of them, the mesh-connected processor arrays model based on single-track switches was proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. Furthermore, the 2 track switch model [2] and the multiple track switch model [3] were proposed to enhance yields and reliabilities of arrays. However, in these models, Simplicity of the routing hardware is somewhat lost because multiple tracks are used for each row and column. In this paper, we present a builtin self-reconstruction approach for mesh-connected processor arrays which are partitioned into sub-arrays each using single-track switches. Spare PEs which are located on the boundaries of the sub-arrays compensate faulty PEs in these sub-arrays. First, we formulate a reconfigulation algorithm for partitioned mesh-arrays using a Hopfield-type neural network, and then its performance for reconfigulation in terms of survival rates and reliabilities of arrays and processing time are investigated by computer simulations. From the results, we can see that high reliabilites are achieved while processing time is a little and hardware overhead (links and switches) required for reconstruction is as same as that for the track switch model. Next, we present a hardware implementation of the neural algorithm so that a built-in self-reconfigurable scheme may be realized.

This paper describes communication traffic characteristics in cellular systems employing the concept of reuse partitioning and Dynamic Channel Assignment. Such systems hava a problem of the spatial unbalance of blocking probability. The objective of this paper is overcoming this problem. To accomplish this objective, we use a method for analyzing communication traffic characteristics. We also show results on traffic characteristics in the systems.

Rain over ocean was observed by a real aperture microwave imaging radar. The radar has a function to record the received power on hit-by-hit base. Since the imaging radar has a wide beam in a plane perpendicular to the flight direction, rain echo and sea surface echo are overlapped in some range gates. In the overlapped range gates, a short-term received power fluctuations appeared. The correlation time of the fluctuation is shorter than those of rain and sea surface echoes. This fluctuation is thought to be due to an interference between rain and sea surface echoes. A computer simulation supports this speculation.

Pitchmatching algorithms are widely used in layout environments where no grid constraints are imposed. However, realistic layouts include multiple grid constraints which facilitate the applications of automatic routing. Hence, pitchmatching algorithms should be extended to those realistic layouts. This paper formulates a pitchmatching problem with multiple grid constraints. An algorithm for solving this problem is constructed as an extension of conventional pitchmatching algorithms. The computational complexity is also discussed in comparison with a conventional naive algorithm. Finally, examples and application results to realistic layouts are presented.

This paper presents a vision-based human interface system that enables a user to move a target object in a 3D CG world by moving his hand. The system can interpret hand motions both in a frame fixed in the world and a frame attached to the user. If the latter is chosen, the user can move the object forward by moving his hand forward even if he has changed his body position. In addition, the user does not have to keep in mind that his hand is in the camera field of view. The active camera system tracks the user to keep him in its field of view. Moreover, the system does not need any camera calibration. The key for the realization of the system with such features is vision algorithms based on the multiple view affine invariance theory. We demon-strate an experimental system as well as the vision algorithms. Human operation experiments show the usefulness of the system.

Recently, ABR has been attracting attention as a new service category of ATM, and the methodology to realize ABR is being actively discussed in the ATM Forum. ABR is expected to become a suitable class for supporting LAN services on ATM networks. To this end, a technical foundation must be established in which bandwidth is effectively utilized and quality is guaranteed. In order for ABR to use a portion of the bandwidth that is not used by high-priority classes (CBR, VBR), it is necessary to appropriately estimate the unused portion of the bandwidth. Due to the fact that the unused portion of the bandwidth in ATM networks fluctuates, such fluctuations must be taken into account. This paper describes ABR connection admission control and design of the congestion detecting point in an ABR buffer using Allan variance of the unused portion of the bandwidth.

This paper shows that a network supplying variable bit rate services can be prevented from becoming congested if each terminal limits the capacity of its connection in terms of its rate of increase. Variable bit rate sources are adequately assessed with two new concepts: the bit rate increase per unit time (acceleration-rate=αbit/sec2) or the bit rate increase ratio (acceleration-ratio=exp (β) ). The dimension of the acceleration-ratio coefficient βis seconds-1. The upper limits α and β are regulated to guarantee the network's QoS. The proposed concepts allow the network state to be accurately estimated and avoid congestion. The proposed method can be applied to ATM networks, Frame Relay networks, Fast Reservation Protocol systems and so on.

We studied effects of 50-200-keV electrons on semiconductor devices using BEASTLI (backscattered electron assisting LSI inspection) method. When irradiating semiconduc-tor devices with such high-energy electrons, we have to note two phenomena. The first is surface charging and the second is device damage. In our study of surface charging, we found that a net positive charge was formed on the device surface. The positive surface charges do not cause serious influence for observation so that we can inspect wafers without problems. The positive surface charging may be brought about because most incident electrons penetrate the device layer and reach the conducting substrate of the semiconductor device. For the device damage, we studied MOS devices which were sensitive to electron-beam irradiation. By applying a 400- annealing to electron-beam irradiated MOS devices, we could restore the initial characteris-tics of MOS devices. However, in order to recover hot-carrier degradation due to neutral traps, we had to apply a 900- annealing to the electron-beam irradiated MOS devices. Thus, BEASTLI could be successfully used by providing an apporopri-ate annealing to the electron-beam irradiated MOS devices.

Many ATM switching modules with high performance have been proposed and analyzed. A development of a large scale ATM switching system (e.g., used as a central switch) is the key to realization of the broadband ISDN. However, the dimension of ATM switching ICs is limited by the technological and physical constraints on VLSI. A multistage switching configuration is one of the promising configurations for a large scale ATM switch. In this paper, we treat a 3-stage switching configuration with no internal bufferes; i.e., bufferless switches are employed at the first and second stages, and output buffered switches at the third stage. A short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on performance of the bufferless switch used at the first two stages. Furthermore, we propose a 4-stage switching configuration with traffic distributors added at the first stage. This switch provides more paths between a pair of input and output ports than the 3-stage switching configuration mentioned above. A few schemes to distribute cells are compared. It is shown that the distributor successfully reduces the deterioration of cell loss probability due to bursty traffic by splitting incoming cells into several switching modules.

A new electron-beam wafer inspection system has been developed. The system has a resolution of 5 nm or better, and is applicable to quarter-micron devices such as 256 Mbit DRAMs. The most remarkable feature of this system is that a specimen stage is built in the objective lens and allows a working distance (WD) of 0. "WD=0"minimizes the effect of lens aberrations, and maximizes the resolving power. Innovative designs to achieve WD=0 are as follows: (1)A large objective lens of 730-mm width 730-mm depth 620-mm height that serves as a specimen chamber, has been developed. (2)A hollow specimen stage made of non-magnetic materials has been developed.It allows the lower pole piece and magnetic coile of the objective lens inside it. (3)Acoustic motors made of non-magnetic materials are em-ployed for use in vacuum.

A new cost model CPO (Cost of Process Ownership) has been proposed. We have already the well known cost model CEO (Cost of Equipment Ownership) [1] which is a cost index assigned independently to individual equipment. However, CPO is basically a cost index assigned to process step in processing flow chart of actual product in a Fab line. Therefore, it is essentially more effective to evaluate the Fab performance such as cost analysis of process steps, estimation of the whole wafer processing cost for specific product, identification of the bottle neck process step or equipment in a Fab line. Further, in designing a high cost-performance factory or in modifying existing factory, it affords important guide such as optimal scales for both factory and equipments with their investment efficiency.

In this paper, we formulate and solve a discrete-time queueing problem that has two potential applications: ATM multiplexers and DQDB networks. We first consider the modeling of an ATM multiplexer. The object of the analysis is a periodic traffic stream (CBR traffic), which is one of the inputs to the multiplexer. As in previous works of the subject, we consider a memoryless background traffic input. Here, in addition to this background traffic, we take into account the influence of a high-priority traffic, which is time-correlated and requires expedited service. We analyze the influence of these two types of traffic on the statistics of the interdeparture time (jitter process) and the delay of the periodic traffic stream. We obtain their distributions in a form of z-transforms, and from these we derive closed form expressions for the average delay and the variance of the interdeparture time. Our results show that the delay and jitter are very sensitive to the burstiness of the high priority traffic arrival process. We next apply our analytical modeling to a DQDB network when some of its stations are driven by CBR sources. We can obtain interesting results concerning the influence of the physical location of a DQDB station on the jitter.

The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.

A performance estimation method has been developed that combines conventional performance evaluation with Bayesian regression analysis. The conventional method is used to estimate performance a priori; this a priori estimate is then updated through Bayesian regression analysis using monitored performance. This method compensates for modeling errors in the conventional technique without recreating complex performance models; it does not require additional traffic measurement or system behavior models. Numerical examples and applications of traffic management in ATM PVC networks have demonstrated its effectiveness.

With the fully depleted ultra-thin-film SOI CMOS, one important issue is controlling the threshold voltage (Vth) while maintaining high speed operation and low power consumption. To control the Vth, applying a bias voltage to the substrate is one of the most practical methods. We suggest a fully depleted ultra-thin-film SOI CMOS with a floating back gate, which is formed at the lower part of the channel field inside the substrate and stores electrons injected into it. This device can eliminate the necessity of an extra circuit or a separate power supply to apply a negative voltage. The silicon wafer direct bonding technique is used to construct this device. With the prototyped devices, we can successfully control the Vth for both the nMOSFET and pMOSFET at around 0.5 V by controlling the quantity of the electric charges injected into the floating back gate.

An analytical framework to study the nonuniformity in geographical distribution of the traffic load in low earth orbit satellite communication systems is presented. The model is then used to evaluate the throughput performance of the system with direct-sequence packet spread-slotted ALOHA multiple-access technique. As the result, it is shown that nonuniformity in traffic makes the characteristics of the system significantly different from the results of uniform traffic case and that the performance of each user varies according to its location. Moreover, the interference reached from users of adjacent satellites is shown to be one of the main factors that limit the performance of system.