Four imperfections encountered in transmitter power control (TPC) for direct sequence code division multiple access (DS/CDMA) cellular mobile communications systems, faulty TPC, finite dynamic range, restricted site diversity, and non-uniform user distribution, are investigated where account is taken of the effect of the propagation constant on the traffic capacity. Computer simulation schemes for traffic capacity estimation under these TPC imperfections are presented. Traffic capacity estimates are produced for a representative DS/CDMA cellular mobile communications system.

This letter proposes a new routing strategy and a design of ATM switches. By partitioning internal links into subgroups based on the bandwidth of a connection request, an ATM switching network which is nonblocking in the wide sense at the connection level can be constructed without the need of internal-link speedup.

In this paper we propose a method of formal verfication of fault-tolerance of sequential machines using regular temporal logic. In this method, fault-tolerant properties are described in the form of input-output sequences in regular temporal logic formulas and they are formally verified by checking if they hold for all possible input-output sequences of the machine. We concretely illustrate the method of its application for formal verification of fail-safeness with an example of a comparator for redundant system. The result of verification shows effectiveness of the proposed method.

A circuit emulation technique in the ATM network becomes necessary to guarantee user requirements similar to QOS grade offered by STM network where small bit error rates and constant delay times are offered. The Head-Of-Line method or other priority control schemes may be considered to provide such service in the ATM network, while it is known to give too inferior quality to non-circuit emulation service traffic. In this paper, we propose a new method called a periodical bandwidth allocation method for the circuit emulation technique. The cells of circuit emulation service traffic are transmitted periodically in our proposal. A periodical interval is determined from both the length of limit delay time of circuit emulation traffic in each switching node and the number of cell arrivals during the limit delay time. To evaluate our method, we consider three kinds of arrival patterns (the best case, the moderate case, and the worst case) for the circuit emulation traffic and a two-state MMPP for modeling the non-circuit emulation traffic. We show performance results in terms of the cell loss probability and the mean delay time in our proposal through analytic and simulation approaches.

An active feedback resonator (AFR) is a kind of circuit which functions as a high unloaded Q resonator. The AFR employs an active feedback loop which compensates for the energy loss of a conventional microwave resonator. Owing to an active element in the AFR, thermal noise should be taken into account when designing the AFR. In order to simplify a circuit design using the AFR we introduced noise temperature (Tn) for the AFR. In addition, we describe the AFR design which gives minimum noise temperature. Finally, the noise temperature, measured in an AFR as a band elimination filter, is compared with the theoretical value to evaluate the AFR.

This paper first clarifies the logic construction of safety control for the operation of a power press and then describes fail-safe dual two-rail system signal processing and fail-safe multiple-valued logic operations as methods for achieving this control as a fail-safe system. It finally shows a circuit for generating fail-safe two-rail run button signals based on ternary logic for concrete operation of the power press and an operation control circuit for confirming brake performance for each cycle of slide operation by using the run button signals. The control circuit uses such multiple-valued logic operations that binary logic signals that do not erroneously go logic 1 are added to a multiple-valued logic signal and the multiple-valued logic signal is converted to a binary logic signal that does not erroneously go logic 1 by a threshold operation.

We propose a high-speed SOI bipolar transistor fabricated using bonding and thinning techniques. It is important to replace SOI area except for devices with thick SiO2 to reduce parasitic capacitance. A thin SOI film with a thin buried layer helps meet this requirement. We formed a 1-µm-thick SOI film with a 0.7-µm-thick buried layer by ion implantation before wafer bonding pulse-field-assisted bonding and selective polishing. Devices were completely isolated by thick SiO2 using a thin SOI film and the LOCOS process. We fabricated epitaxial base transistors (EBTs) on bonded SOI. Our transistors had a cutoff frequency of 32 GHz.

This paper proposes an ATM traffic management method that utilizes a deterministic source traffic descriptor, a deterministic Usage Parameter Control (UPC) algorithm and a conservative statistical bandwidth allocation method all of which were developed considering the Cell Delay Variation (CDV) typically experienced in ATM networks. For the source traffic descriptor, sliding time interval-type descriptors are proposed. A newly-structured UPC method which combines a sliding window-type circuit and a 2-phase credit window type circuit is proposed. The method is precise and accurate and requires only a small amount of hardware. The proposed parameter conversion method considers the CDV generated between User and UPC point. A bandwidth allocation method based on the worst clumping pattern and UPC output pattern is proposed. The network efficiency degradation caused by CDV is calculated. This traffic management method not only guarantees the QOS of all connections but also allows for large statistical multiplexing gains. The proposed method will, therefore, make it possible to create a more effective B-ISDN, one that can offer cost-effective broadband VBR services.

Robust-fault tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of faults in digital system. There are many cases where the safety of digital control systems can be maintained if the property is satisfied. In this paper, robust-fault-tolerant three-valued arithmetic modules such as an adder and a multiplier are proposed. The positive and negative integers are represented by the number of 1's and 1's, respectively. The design concept of the arithmetic modules is that a fault makes linearly additive effect with a small value to the final result. Each arithmetic module consists of identical submodules linearly connected, so that multi-stage structure is formed to generate the final output from the last submodule. Between the input and output digits in the submodule some simple functional relation is satisfied with respect to the number of 1's and 1's. Moreover, the output digit value depends on very small portion of the submodules including the input digits. These properties make the linearly additive effect with a small value to the final result in the arithmetic modules even if multiple faults are occurred at the input and output of any gates in the submodules. Not only direct three-valued representation but also the use of three-valued logic circuits is inherently suitable for efficient implementation of the arithmetic VLSI system. The evaluation of the robust-fault-tolerant three-valued arithmetic modules is done with regard to the chip size and the speed using the standard CMOS design rule. As a result, it is made clear that the chip size can be greatly reduced.

Broadband ISDN based on ATM technologies is expected to offer enhanced and sophisticated services to customers. Since ATM will first be introduced in the business communication world, it will be worth to discuss the future image of desirable ATM customer premises network (CPN). In this paper, we first consider the possible migration scenario of Broadband CPN and some important requirements for the realization of the scenario. Then, we discuss the key issues to be solved for future ATM-CPN, which include network topology, traffic control and connectionless communication services.

Free choice nets are a class of Petri nets, which can represent the substantial features of systems by modeling both choice and concurrency. And in the modelling and design of a large number of concurrent systems, live and safe free choice nets (LSFC nets) have been explored their structural characteristics. On the other hand, state machine decomposable nets (SMD nets) are a class of Petri nets which can be decomposed by a set of strongly connected state machines (S-decomposition). State machine allocatable nets (SMA nets) are a well-behaved class of SMD nets. Of particular interest is the relation between free choice nets and SMA nets such that a free choice net has a live and safe marking if and only if the net is an SMA net. That is, the structure of an LSFC net is an SMA net. Recently, the structure of SMA net has been completely characterized by the authors based on an S-decomposition. In other words, a necessary and sufficient condition for a net to be an SMA net is obtained in terms of the net structure where synchronization between strongly connected state machine components (S-components) has been clarified. Unfortunately, it requires tremendous amount of time and spaces to decide a given net to be an SMA net by applying the condition directly. Moreover, there exist no efficient algorithm to decide the liveness and safeness of a given SMA net that lessens the usefulness of decomposition techniques. In this paper, we consider efficient polynomial order algorithms to decide whether a given net is a live and safe SHA net.

A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.

This paper surveys the developments and achievements of teletraffic studies in Japan. It briefly covers the period preceding 1970, then focuses on the period after 1970. Rather than attempting to cover the entire field of teletraffic engineering, it places its emphasis on basic models.

Cell losses due to statistical multiplexing of bursty traffic in ATM networks tend to be in clusters rather than uniformly scattered. Since the quality of service for users is quite sensitive to such bursty losses, it is necessary to characterize the temporal behavior of cell loss. This paper reports results obtained from investigating overload period and underload period in an ATM multiplexer with heterogeneous burst traffic input, using a bufferless model. The overload period is defined as the time interval when the instantaneous bit rate exceeds the output link capacity. With the bufferless model, we assume that all the instantaneous bit rate exceeding the link capacity is lost, and the loss rate is called "virtual cell loss probability". The virtual cell loss probability during the overload period, average overload period and underload period durations are analyzed. Numerical results show that the cell loss probability in overload periods and the average duration of overload periods (normalized by burst duration) are not very sensitive to link load or average rate/peak rate ratio of the burst, and that they are approximately on the order of peak bandwidth/link capacity ratio for the multiplexed burst. Furthermore, it is also shown that the mean underload duration is simply given as the inverse of the overall cell loss probability multiplied by the constant value inherently determined by peak bandwidth and link capacity. With these observations, applications to the call acceptance control using these measures are also presented.

SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.

A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.

Charges in buried oxide layers formed by wafer bonding were evaluated by capacitance-voltage (C-V) measurements. In this study, silicon-insulator-silicon (SIS) and metal-oxide-silicon (MOS) capacitors were fabricated on bonded wafers. For analyzing C-V curves of SIS structures, C-V simulation programs were developed. From the analysis, we conclude that approximately 2 1011/cm2 negative charges were distributed uniformly in the oxide. The effect of the experimental conditions during wafer bonding on generated charges in buried oxides is also discussed.

This letter proposes a new UPC (Usage Parameter Control) method suitable for monitoring/controlling the ATM cell streams of VCs (Virtual Channels) and VPs (Virtual Paths) specified with a wide-range of traffic parameter values. The method, named the 2-phase T-X method, combines two credit window type monitoring circuits that are shifted in phase by T/2. The proposed method achieves the best of both the DB and T-X methods. Its cell mis-policing rate is very low (equivalent to that of the DB-method) while its minimal hardware requirements are equal to those of the T-X method. The proposed method ensures more effective network resource (link) utilization. As a result, the proposed method is shown to be a credible UPC technique for handling broadband VBR (Variable Bit Rate) traffic in ATM based multimedia networks.

In the present paper we present a mathematical theory for the transient analysis of probabilistic models relevant to communication networks. First we review the z-transform method, the matrix method, and the Laplace transform, as applied to a class of birth-and-death process model that is relevant to characterize network traffic sources. We then show how to develop transient solutions in terms of the eigenvalues and spectral expansions. In the latter half the paper we develop a general theory to solve dynamic behavior of statistical multiplexer for multiple types of traffic sources, which will arise in the B-ISDN environment. We transform the partial differential equation that governs the system into a concise form by using the theory of linear operator. We present a closed form expression (in the Laplace transform domain) for transient solutions of the joint probability distribution of the number of on sources and buffer content for an arbitrary initial condition. Both finite and infinite buffer capacity cases are solved exactly. The essence of this general result is based on the unique determination of unknown boundary conditions of the probability distributions. Other possible applications of this general theory are discussed, and several problems for future investigations are identified.

A new design method is proposed for realizing a hypercube network (HC) structured multicomputer system on a wafer using wafer-scale integration (WSI). The probability that an HC can be constructed on a wafer is higher in this method than in the conventional method; this probavility is called a construction probability. We adopt the FUSS method for the processor (PE) address allocation in our desing because it has a high success probability in the allocation. Even if the design renders the address allocation success probalility hegher, it is of no use if it makes either the maximum wiring length between PEs or the array size (wiring area) larger. A new wiring channel structure capable of connecting PEs on a wafer is proposed in this paper, where a channel, called a basic channel, is used. A one-dimensional-array sub-HC row network (RN) or column networks (CN) can be constructed using the basic channel. The sub-HC construction method, which embeds wirings into the basic channel, is also proposed. It requires almost the same wiring width as conventional method. However, it has an advantage in that maximum wiring length between PEs can be about half that of the conventional method. If PEs must be shifted in the case of PE defects, they can be shifted and connected to the basic channel using other PE shifting channels, and an RN or CN can be constructed. The maximum wiring length between PEs, array size, and construction probability will also be derived, and it will be shown that the proposed design is superior to the conventional one.