In this paper, we first propose two batch blind source separation and equalization algorithms based on support vector regression (SVR) for linear time-invariant multiple input multiple output (MIMO) systems. The proposed algorithms combine the conventional cost function of SVR with error functions of classical on-line algorithm for blind equalization: both error functions of constant modulus algorithm (CMA) and radius directed algorithm (RDA) are contained in the penalty term of SVR. To recover all sources simultaneously, the cross-correlations of equalizer outputs are included in the cost functions. Simulation experiments show that the proposed algorithms can recover all sources successfully and compensate channel distortion simultaneously. With the use of iterative re-weighted least square (IRWLS) solution of SVR, the proposed algorithms exhibit low computational complexity. Compared with traditional algorithms, the new algorithms only require fewer samples to achieve convergence and perform a lower residual interference. For multilevel signals, the single algorithms based on constant modulus property usually show a relatively high residual error, then we propose two dual-mode blind source separation and equalization schemes. Between them, the dual-mode scheme based on SVR merely requires fewer samples to achieve convergence and further reduces the residual interference.

This paper proposes a regulated transport network design algorithm for IP over a dense wavelength division multiplex (DWDM) network. When designing an IP over DWDM network, the network operator should consider not only cost-effectiveness and physical constraints such as wavelength colors and chromatic dispersion but also operational policies such as resilience, quality, stability, and operability. For considering the above polices, we propose to separate the network design algorithm based on a geographical resolution; the policy-based regulated intra-area is designed based on this resolution, and the cost-optimal inter-area is then designed separately, and finally merged. This approach does not necessarily yield a strict optimal solution, but it covers network design work done by humans, which takes a vast amount of time and requires a high skill level. For efficient geographical resolution, we also present fast graph mining algorithm, which can solve NP-hard subgraph isomorphism problem within the practical time. We prove the sufficiency of the resulting network design for the above polices by visualizing the topology, and also prove that the penalty of applying the approach is trivial.

Erasure codes have been considered as one of the most promising techniques for data reliability enhancement and storage efficiency in modern distributed storage systems. However, erasure codes often suffer from a time-consuming coding process which makes them nearly impractical. The opportunity to solve this problem probably rely on the parallelization of erasure-code-based application on the modern multi-/many-core processors to fully take advantage of the adequate hardware resources on those platforms. However, the complicated data allocation and limited I/O throughput pose a great challenge on the parallelization. To address this challenge, we propose a general multi-threaded parallel coding approach in this work. The approach consists of a general multi-threaded parallel coding model named as MTPerasure, and two detailed parallel coding algorithms, named as sdaParallel and ddaParallel, respectively, adapting to different I/O circumstances. MTPerasure is a general parallel coding model focusing on the high level data allocation, and it is applicable for all erasure codes and can be implemented without any modifications of the low level coding algorithms. The sdaParallel divides the data into several parts and the data parts are allocated to different threads statically in order to eliminate synchronization latency among multiple threads, which improves the parallel coding performance under the dummy I/O mode. The ddaParallel employs two threads to execute the I/O reading and writing on the basis of small pieces independently, which increases the I/O throughput. Furthermore, the data pieces are assigned to the coding thread dynamically. A special thread scheduling algorithm is also proposed to reduce thread migration latency. To evaluate our proposal, we parallelize the popular open source library jerasure based on our approach. And a detailed performance comparison with the original sequential coding program indicates that the proposed parallel approach outperforms the original sequential program by an extraordinary speedups from 1.4x up to 7x, and achieves better utilization of the computation and I/O resources.

The conventional generalized spatial modulation (GSM) simultaneously activates multiple transmit antennas in order to improve the spectral efficiency of the original SM. In this letter, to lessen the hardware burden of the multiple RF chains, we provide a new scheme that is designed by combining the GSM scheme using only two active antennas with quaternary quasi-orthogonal sequences of a length of two. Compared with the other SM schemes, the proposed scheme has significant benefits in average error performances and/or their hardware complexities of the RF systems.

The existing methods to estimate satellite attitude by using radar cross section (RCS) sequence suffer from problems such as low precision, computation complexity, etc. To overcome these problems, a novel model of satellite attitude estimation by the local maximum points of the RCS sequence is established and can reduce the computational time by downscaling the dimension of the feature vector. Moreover, a particle swarm optimization method is adopted to improve efficiency of computation. Numerical simulations show that the proposed method is robust and efficient.

Protein-Protein Interaction Extraction (PPIE) from biomedical literatures is an important task in biomedical text mining and has achieved great success on public datasets. However, in real-world applications, the existing PPI extraction methods are limited to label effort. Therefore, transfer learning method is applied to reduce the cost of manual labeling. Current transfer learning methods suffer from negative transfer and lower performance. To tackle this problem, an improved TrAdaBoost algorithm is proposed, that is, relative distribution is introduced to initialize the weights of TrAdaBoost to overcome the negative transfer caused by domain differences. To make further improvement on the performance of transfer learning, an approach combining active learning with the improved TrAdaBoost is presented. The experimental results on publicly available PPI corpora show that our method outperforms TrAdaBoost and SVM when the labeled data is insufficient,and on document classification corpora, it also illustrates that the proposed approaches can achieve better performance than TrAdaBoost and TPTSVM in final, which verifies the effectiveness of our methods.

LSIs are generally designed through four stages including architectural design, logic design, circuit design, and physical design. In architectural design and logic design, designers describe their target hardware in RTL. However, they generally use different languages for each phase. Typically a general purpose programming language such as C or C++ and a hardware description language such as Verilog HDL or VHDL are used for architectural design and logic design, respectively. That is time-consuming way for designing a hardware and more efficient design environment is required. In this paper, we propose a new hardware modeling and high-speed simulation environment for architectural design and logic design. Our environment realizes writing and verifying hardware by one language. The environment consists of (1) a new hardware description language called ArchHDL, which enables to simulate hardware faster than Verilog HDL simulation, and (2) a source code translation tool from ArchHDL code to Verilog HDL code. ArchHDL is a new language for hardware RTL modeling based on C++. The key features of this language are that (1) designers describe a combinational circuit as a function and (2) the ArchHDL library realizes non-blocking assignment in C++. Using these features, designers are able to write a hardware transparently from abstracted level description to RTL description in Verilog HDL-like style. Source codes in ArchHDL is converted to Verilog HDL codes by the translation tool and they are used to synthesize for FPGAs or ASICs. As the evaluation of our environment, we implemented a practical many-core processor in ArchHDL and measured the simulation speed on an Intel CPU and an Intel Xeon Phi processor. The simulation speed for the Intel CPU by ArchHDL achieves about 4.5 times faster than the simulation speed by Synopsys VCS. We also confirmed that the RTL simulation by ArchHDL is efficiently parallelized on the Intel Xeon Phi processor. We convert the ArchHDL code to a Verilog HDL code and estimated the hardware utilization on an FPGA. To implement a 48-node many-core processor, 71% of entire resources of a Virtex-7 FPGA are consumed.

We propose and demonstrate a method that can demultiplex an optical OFDM signal with various capacity based on time lens-based optical Fourier transform. The proposed tunable optical OFDM signal demultiplexer is composed of a phase modulator and a tunable chromatic dispersion emulator. The spectrum of the variable capacity OFDM signal is transformed into Nyquist time-division multiplexing pulses with the optical Fourier transform, and the OFDM sub-carrier channels are dumultiplexed in the time-domain. We also propose a simple method for approximating and generating quadratic waveform to drive the phase modulator. After explaining the operating principle of the method and the design of some parameters in detail, we show successful demultiplexing of 4×8 and 4×10 Gbit/s optical OFDM signals with our proposed method as the preliminary investigation results.

This paper proposes a novel method for two-dimensional (2-D) direction-of-arrival (DOA) estimation of multiple signals employing a sparse L-shaped array structured by a sparse linear array (SLA), a sparse uniform linear array (SULA) and an auxiliary sensor. In this method, the elevation angles are estimated by using the SLA and an efficient search approach, while the azimuth angle estimation is performed in two stages. In the first stage, the rough azimuth angle estimates are obtained by utilizing a noise-free cross-covariance matrix (CCM), the estimated elevation angles and data from three sensors including the auxiliary sensor. In the second stage, the fine azimuth angle estimates can be achieved by using the shift-invariance property of the SULA and the rough azimuth angle estimates. Without extra pair-matching process, the proposed method can achieve automatic pairing of the 2-D DOA estimates. Simulation results show that our approach outperforms the compared methods, especially in the cases of low SNR, snapshot deficiency and multiple sources.

Concurrent transmission (CT) is a revolutionary multi-hop protocol that significantly improves the MAC- and network-layer efficiency by allowing synchronized packet collisions. Although its superiority has been empirically verified, there is still a lack of studies on how the receiver survives such packet collisions, particularly in the presence of the carrier frequency offsets (CFO) between the transmitters. This work rectifies this omission by providing a comprehensive evaluation of the physical-layer receiver performance under CT, and a theoretical analysis on the fading duration of the beating effect resulting from the CFO. The main findings from our evaluations are the following points. (1) Beating significantly affects the receiver performance, and an error correcting mechanism is needed to combat the beating. (2) In IEEE 802.15.4 systems, the direct sequence spread spectrum (DSSS) plays such a role in combatting the beating. (3) However, due to the limited length of DSSS, the receiver still suffers from the beating if the fading duration is too long. (4) On the other hand, the basic M-ary FSK mode of IEEE 802.15.4g is vulnerable to CT due to the lack of error correcting mechanism. In view of the importance of the fading duration, we further theoretically derive the closed form of the average fading duration (AFD) of the beating under CT in terms of the transmitter number and the standard deviation of the CFO. Moreover, we prove that the receiver performance can be improved by having higher CFO deviations between the transmitters due to the shorter AFD. Finally, we estimate the AFD in the real system by actually measuring the CFO of a large number of sensor nodes.

The problem of evaluating the matrix polynomial I+A+A2+…+AN-1 with a reduced number of matrix multiplications has long been considered. Several algorithms have been proposed for this problem, which find a procedure requiring O(log N) matrix multiplications for a given N. Among them, the hybrid algorithm based on the double-base representation of N, i.e., using mixed radices 2 and 3, proposed by Dimitrov and Cooklev is most efficient. It has been suggested by them that the use of higher radices would not bring any more efficient algorithms. In this paper, we show that we can derive more efficient algorithms by using higher radices, and propose several efficient algorithms.

This paper proposes a genetic algorithm (GA) based design method for arbitrarily-shaped resonant elements that offer enhanced reflectarray antenna performance. All elements have the specified phase property over the range of 360°, and also have dual-polarization and low cross-polarization properties for better reflectarray performance. In addition, the proposal is suitable for linear-to-circular polarization conversion elements. Thus, polarizer reflectarray elements are also presented in this paper. The proposed elements are validated using both numerical simulations and experiments.

An area-efficient FPGA-based annealing processor that is based on Ising model is proposed. The proposed processor eliminates random number generators (RNGs) and temperature schedulers, which are the key components in the conventional annealing processors and occupying a large portion of the design. Instead, a shift-register-based spin flipping scheme successfully helps the Ising model from stucking in the local optimum solutions. An FPGA implementation and software-based evaluation on max-cut problems of 2D-grid torus structure demonstrate that our annealing processor solves the problems 10-104 times faster than conventional optimization algorithms to obtain the solution of equal accuracy.

Field-programmable gate array (FPGA) devices are applied for accelerating specific calculations and reducing power consumption in a wide range of areas. One of the challenges associated with FPGAs is reducing static power for enforcing their power effectiveness. We propose a method involving fine-grained reconfiguration of body biases of logic and net resources to reduce the static power of FPGA devices. In addition, we develop an FPGA device called Flex Power FPGA with SOTB technology and demonstrate its power reduction function with a 32-bit counter circuit. In this paper, we describe the construction of an experimental platform to precisely evaluate power consumption and the maximum operating frequency of the device under various operating voltages and body biases with various practical circuits. Using the abovementioned platform, we evaluate the Flex Power FPGA chip at operating voltages of 0.5-1.0 V and at body biases of 0.0-0.5 V. In the evaluation, we use a 32-bit adder, 16-bit multiplier, and an SBOX circuit for AES cryptography. We operate the chip virtually with uniformed body bias voltage to drive all of the logic resources with the same threshold voltage. We demonstrate the advantage of the Flex Power FPGA by comparing its performance with non-reconfigurable biasing.

A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation phase using ring amplifier and SAR quantizer. The proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 95.70dB is achieved while a sinusoid -1dBFS input is sampled at 60MS/s for the bandwidth is BW=470kHz. The power consumption of the analog part in the modulator is 1.67mW while the supply voltage is 1.2V.

An optimal design method for a sub-ranging Analog-to-Digital Converter (ADC) based on stochastic comparator is demonstrated by performing theoretical analysis of random comparator offset voltages. If the Cumulative Distribution Function (CDF) of the comparator offset is defined appropriately, we can calculate the PDFs of the output code and the effective resolution of a stochastic comparator. It is possible to model the analog-to-digital conversion accuracy (defined as yield) of a stochastic comparator by assuming that the correlations among the number of comparator offsets within different analog steps corresponding to the Least Significant Bit (LSB) of the output transfer function are negligible. Comparison with Monte Carlo simulation verifies that the proposed model precisely estimates the yield of the ADC when it is designed for a reasonable target yield of >0.8. By applying this model to a stochastic comparator we reveal that an additional calibration significantly enhances the resolution, i.e., it increases the Number of Bits (NOB) by ∼ 2 bits for the same target yield. Extending the model to a stochastic-comparator-based sub-ranging ADC indicates that the ADC design parameters can be tuned to find the optimal resource distribution between the deterministic coarse stage and the stochastic fine stage.

An efficient handover measurement technique is proposed for millimeter-wave (mm-wave) cellular systems with directional antenna beams. As the beam synchronization signal (BSS) carries the cell ID and the beam ID in a hierarchal manner, handover events (interbeam handover and intercell handover) are distinguished at the physical layer. The proposed signal metrics are shown to be effective in detecting the beam boundaries and cell boundaries in mm-wave cellular systems, which allows to distinguish interbeam handover from intercell handover. The proposed handover measurement technique is shown to reduce the processing time significantly using the proposed signal metrics produced by the BSS.

Two different types of representations, such as an image and its manually-assigned corresponding labels, generally have complex and strong relationships to each other. In this paper, we represent such deep relationships between two different types of visible variables using an energy-based probabilistic model, called a deep relational model (DRM) to improve the prediction accuracies. A DRM stacks several layers from one visible layer on to another visible layer, sandwiching several hidden layers between them. As with restricted Boltzmann machines (RBMs) and deep Boltzmann machines (DBMs), all connections (weights) between two adjacent layers are undirected. During maximum likelihood (ML) -based training, the network attempts to capture the latent complex relationships between two visible variables with its deep architecture. Unlike deep neural networks (DNNs), 1) the DRM is a totally generative model and 2) allows us to generate one visible variables given the other, and 2) the parameters can be optimized in a probabilistic manner. The DRM can be also fine-tuned using DNNs, like deep belief nets (DBNs) or DBMs pre-training. This paper presents experiments conduced to evaluate the performance of a DRM in image recognition and generation tasks using the MNIST data set. In the image recognition experiments, we observed that the DRM outperformed DNNs even without fine-tuning. In the image generation experiments, we obtained much more realistic images generated from the DRM more than those from the other generative models.

In this paper, we propose an indoor localization method that uses only the Received Signal Strength Indicator (RSSI) of signals transmitted from wireless beacons. The beacons use three-element array antennas, and the position of the receiving terminal is estimated by using multiple DOD information. Each beacon transmits four beacon signals with different directivities by feeding signals to the three-element array antennas via 180-degree and 90-degree hybrids. The correlation matrix of the propagation channels is estimated from just the strength of the signals, and the DOD is estimated from the calculated correlation matrix. For determining the location of the receiving terminal, the existence probability function is introduced. Experiments show that the proposed method attains lower position estimation error than the conventional method.

Precise determination of antenna phase centers is crucial to reduce the uncertainty in gain when employing the three-antenna method, particularly when the range distances are short-such as a 3-m radio anechoic chamber, where the distance between the phase centers and the open ends of an aperture antenna (the most commonly-used reference) is not negligible compared with the propagation distance. An automatic system to determine the phase centers of aperture antennas in a radio anechoic chamber is developed. In addition, the absolute gain of horn antennas is evaluated using the three-antenna method. The phase centers of X-band pyramidal horns were found to migrate up to 18mm from the open end. Uncertainties in the gain were evaluated in accordance with ISO/IEC Guide 93-3: 2008. The 95% confidence interval of the horn antenna gain was reduced from 0.57 to 0.25dB, when using the phase center location instead of the open end. The phase centers, gains, polarization, and radiation patterns of space-borne antennas are measured: low and medium-gain X-band antennas for an ultra small deep space probe employing the polarization pattern method with use of the horn antenna. The 95% confidence interval in the antenna gain decreased from 0.74 to 0.47dB.