This paper proposes a windowed-sinc function based peak-to-average power ratio (PAPR) reduction scheme for applying the polar transmitter techniques to orthogonal frequency division multiplexing (OFDM), where the high PAPR problem occurs. The proposed algorithm mitigates the effect of excessive suppression due to successive peaks or relatively high peaks of a signal, which is often observed when applying the conventional peak windowing scheme. The bit error rate (BER) and error vector magnitude (EVM) performances are measured for various window types and lengths. The simulation results demonstrate that the proposed algorithm achieves significant improvement in terms of BER and PAPR reduction performance while maintaining similar spectrum performance compared to the conventional peak windowing scheme.

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

One-time signature schemes have been used as an important cryptographic tool for various applications. To generate a signature on a message, the state-of-the-art one-time signature requires roughly one hash function evaluation and one modular multiplication. We propose a new one-time signature scheme for short messages that needs only one integer multiplication (i.e., without modular reduction or hash function evaluation). Theoretically, our construction is based on a generic transformation from identification protocols secure against active attacks into secure one-time signature schemes for short messages, where the Fiat-Shamir technique is not used. To obtain efficient instantiation of the transformation, we prove that the GPS identification protocol is secure against active attacks, which may be of independent interest.

The tag collection algorithm in ISO/IEC 18000-7 has difficulty in collecting data from massive numbers of active RFID tags in a timely manner, so it should be improved to allow successful application in a wide variety of industrial fields. We propose two novel methods, a reduced-message method to improve the performance of data-tag collection and an efficient-sleep method to improve the performance of ID-tag collection. The reduced-message method decreases the slot size for a tag response by reducing the response size from the tag and reduces the number of commands issued from the reader. The efficient-sleep method utilizes redundant empty slots within the frame period to transmit sleep commands to the tags collected previously. We evaluated the performance improvement of tag collection by the proposed methods experimentally using an active RFID reader and 60 tags that we prepared for this study. The experimental results showed that the reduced-message method and the efficient-sleep method decreased the average tag collection time by 16.7% for data-tag collection and 9.3% for ID-tag collection compared with the standard tag collection. We also developed a simulation model for the active RFID system, reflecting the capture effect in wireless communication, and performed simulations to evaluate the proposed methods with a massive number of tags. The simulation results with up to 300 tags confirmed that the proposed methods could improve the tag collection performance, confirming the experimental results, even with larger numbers of tags.

This letter provides a tight upper bound on the bit error rate (BER) over the Nakagami-m fading channel for the dual carrier modulation (DCM) scheme, which is adopted by the multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband (UWB) system. Its tightness is verified with the existing result for Rayleigh fading channel, i.e., for m=1, which would be also valid for a more general fading environment.

It is important to find an efficient design-for-testability methodology that satisfies both security and testability, although there exists an inherent contradiction between security and testability for digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR-equivalents). However, SR-equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those SR-equivalent scan circuits, we introduce a differential-behavior equivalent relation and clarify the number of SR-equivalent scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.

The development of the electricity market enables us to provide electricity of varied quality and price in order to fulfill power consumers' needs. Such customers choices should influence the process of adjusting power generation and spinning reserve, and, as a result, change the structure of a unit commitment optimization problem (UCP). To build a unit commitment model that considers customer choices, we employ fuzzy variables in this study to better characterize customer requirements and forecasted future power loads. To measure system reliability and determine the schedule of real power generation and spinning reserve, fuzzy Value-at-Risk (VaR) is utilized in building the model, which evaluates the peak values of power demands under given confidence levels. Based on the information obtained using fuzzy VaR, we proposed a heuristic algorithm called local convergence-averse binary particle swarm optimization (LCA-PSO) to solve the UCP. The proposed model and algorithm are used to analyze several test systems. Comparisons between the proposed algorithm and the conventional approaches show that the LCA-PSO performs better in finding the optimal solutions.

This paper provides conceptual and experimental analysis of a new approach in the study of kanji, our “Learner's Visualization (LV) Approach”. In a previous study we found that the LV Approach assists beginning learners in significantly updating their personal kanji deconstruction visualization. Additionally, in another study our findings provided evidence that beginning learners also receive a significant impact in the ability to acquire vocabulary. In this study, our research problem examines how beginning and intermediate students use visualization to cognitively deconstruct (divide) kanji in different ways, and how this affects their learning progress. We analyze the cognitive differences in how kanji learners explore and deconstruct novel kanji while using the LV Approach and how these differences affect their learning process while using the LV Approach. During the learning experience, our LILES System (Learner's Introspective Latent Envisionment System), based on the LV Approach, guides learners to choose from a set of possible “kanji deconstruction layouts” (layouts showing different ways in which a given kanji can be divided). The system then assists learners in updating their “kanji deconstruction level” (the average number of parts they visualize within kanji according to their current abilities). Statistical analysis based on achieved performance was conducted. The analysis of our results proves that there are cognitive differences: beginners deconstruct kanji into more parts (“blocks”) than intermediate learners do, and while both improve their kanji deconstruction scores, there is a more significant change in “kanji deconstruction level” in beginners. However, it was also found that intermediate learners benefit more in “kanji retention score” compared with beginners. Suggestions for further research are provided.

We investigate electronic mitigation of linear and nonlinear fibre impairments and compare various digital signal processing techniques, including electronic dispersion compensation (EDC), single-channel back-propagation (SC-BP) and back-propagation with multiple channel processing (MC-BP) in a nine-channel 112 Gb/s PM-mQAM (m=4,16) WDM system, for reaches up to 6,320 km. We show that, for a sufficiently high local dispersion, SC-BP is sufficient to provide a significant performance enhancement when compared to EDC, and is adequate to achieve BER below FEC threshold. For these conditions we report that a sampling rate of two samples per symbol is sufficient for practical SC-BP, without significant penalties.

In this paper, we propose a simple but effective way of improving the performance of channel estimation (CE) for pilot cyclic prefixed single carrier (PCP-SC) system. The proposed method utilizes the property that the shifting signal of the PCP pilot signal can also be utilized to estimate the channel information. The receiver can continuously estimate the channel information by just shifting the received pilot signal. Regardless of the signal-to-noise ratio (SNR) and the pilot type, the proposed method can achieve about a 1.72 dB performance gain in terms of the mean squared error (MSE) of channel estimation with a slight increase in computational complexity. The BER performance with the proposed CE improvement are evaluated in a multipath fading channel using a zero-forcing (ZF) equalizer and an minmum mean squared error (MMSE) equalizer by computer simulation. It is shown that the proposed CE improvment method using an MMSE equalizer which has an unbiased vlaue of noise variance (NV) estimator gives a promising BER performance. The proposed method also benefits the estimation of the SNR for the single carrier system.

This paper presents an accurate and systematic method to simulate the interference imposed on the input/output (I/O) ports of electronic equipment under the electrical fast transients/burst (EFT/B) test. The equivalent circuit of the EFT/B generator and the coupling clamp are modeled respectively. Firstly, a transfer function (TF) of the EFT pulse-forming network is constructed with the latent parameters based on circuit theory. In the TF, two negative real parameters characterize the non-oscillation process of the network while one complex conjugate pair characterizes the damping-oscillation process. The TF of the pulse-forming network is therefore synthesized in the equivalent circuit of the EFT/B generator. Secondly, the standard coupling clamp is modeled based on the scatter (S) parameter obtained by using a vector network analyzer. By applying the vector fitting method during the rational function approximation, a macromodel of the coupling clamp can be obtained and converted to a Spice compatible equivalent circuit. Based on the aforementioned procedures, the interference imposed on the I/O ports can be simulated. The modeling methods are validated experimentally, where the interference in differential mode and common mode is evaluated respectively.

A safe prime p is a prime such that (p-1)/2 is also a prime. A primality test or a safe primality test is normally a combination of trial division and a probabilistic primality test. Since the number of small odd primes used in the trial division affects the performance of the combination, researchers have studied how to obtain the optimal number of small odd primes to be used in the trial division and the expected running time of the combination for primality tests. However, in the case of safe primality tests, the analysis of the combination is more difficult, and thus no such results have been given. In this paper, we present the first probabilistic analysis on the expected running time and the optimal number of small odd primes to be used in the trial division for optimizing the tests. Experimental results show that our probabilistic analysis estimates the behavior of the safe primality tests very well.

Although a large number of query processing algorithms in spatial network database (SNDB) have been studied, there exists little research on route-based queries. Since moving objects move only in spatial networks, route-based queries, like in-route nearest neighbor (IRNN), are essential for Location-based Service (LBS) and Telematics applications. However, the existing IRNN query processing algorithm has a problem in that it does not consider time and space constraints. Therefore, we, in this paper, propose IRNN query processing algorithms which take both time and space constraints into consideration. Finally, we show the effectiveness of our IRNN query processing algorithms considering time and space constraints by comparing them with the existing IRNN algorithm.

This paper develops planar circuit filters consisting of arbitrarily-shaped conductor patches and slots on a conductor-backed dielectric substrate, which are designed by an optimization technique based on the genetic algorithm. The developed filter has multiple resonators and their mutual couplings in the limited space by using both sides of the substrate, so that its compactness is realized. We first demonstrate the effectiveness of the present filter structure from some design samples numerically and experimentally. Then as a practical application, we design compact UWB filters, and their filter characteristics are verified from the measurements.

The Voronoi game is a two-person perfect information game modeling a competitive facility location. The original version of the game is played on a continuous domain. Only two special cases (1-dimensional case and 1-round case) have been extensively investigated. Recently, the discrete Voronoi game of which the game arena is given as a graph was introduced. In this note, we give a complete analysis of the discrete Voronoi game on a path. There are drawing strategies for both the first and the second players, except for some trivial cases.

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

This letter proposes a new scheduling method to improve scheduling efficiency of EPON. The proposed method uses a credit pool for each optical network unit (ONU) and for each service class. For high scheduling efficiency, the credit pool of an ONU can be negative amount to utilize the unused ONU credits. Also the proposed method dynamically excludes the lowest service class from scheduling to decrease a transmission cycle length. Using simulations, we show that the proposed method is better than the existing methods in mean delay.

A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1 MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18 µm CMOS process with 1.0 V supply voltage. The proposed bootstrapped analog switch reduced the maximum VGS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8 dB when the capacitance of its gate node is 100 fF, and this improvement was maximized when the capacitance of its gate node increases.

Although the Marching Cube (MC) algorithm is very popular for displaying images of voxel-based objects, its slow surface extraction process is usually considered to be one of its major disadvantages. It was pointed out that for the original MC algorithm, we can limit vertex calculations to once per vertex to speed up the surface extraction process, however, it did not mention how this process could be done efficiently. Neither was the reuse of these MC vertices looked into seriously in the literature. In this paper, we propose a “Group Marching Cube” (GMC) algorithm, to reduce the time needed for the vertex identification process, which is part of the surface extraction process. Since most of the triangle-vertices of an iso-surface are shared by many MC triangles, the vertex identification process can avoid the duplication of the vertices in the vertex array of the resultant triangle data. The MC algorithm is usually done through a hash table mechanism proposed in the literature and used by many software systems. Our proposed GMC algorithm considers a group of voxels simultaneously for the application of the MC algorithm to explore interesting features of the original MC algorithm that have not been discussed in the literature. Based on our experiments, for an object with more than 1 million vertices, the GMC algorithm is 3 to more than 10 times faster than the algorithm using a hash table. Another significant advantage of GMC is its compatibility with other algorithms that accelerate the MC algorithm. Together, the overall performance of the original MC algorithm is promoted even further.

Identifying the statistical independence of random variables is one of the important tasks in statistical data analysis. In this paper, we propose a novel non-parametric independence test based on a least-squares density ratio estimator. Our method, called least-squares independence test (LSIT), is distribution-free, and thus it is more flexible than parametric approaches. Furthermore, it is equipped with a model selection procedure based on cross-validation. This is a significant advantage over existing non-parametric approaches which often require manual parameter tuning. The usefulness of the proposed method is shown through numerical experiments.