A Java execution environment is implemented, in which a hardware engine is operated in parallel with an embedded processor. This pair of hardware facilities together with an additional software kernel are devised for existing embedded systems, so as to execute Java applications more efficiently in such a way that 39 instructions are added to the original Java Virtual Machine to implement the software kernel. The exploration of design parameters is also attempted to attain a low hardware cost and high performance. The proposed hardware engine of a 6-stage pipeline can be integrated in a single chip using 30 k gates together with the instruction and data cache memories. The proposed approach improves the execution speed by a factor of 5 in comparison with the J2ME software implementation.

In this paper, we propose a fault-tolerance mechanism for microprocessors, which detects transient faults and recovers from them. The investigation of fault-tolerance techniques for microprocessors is driven by two issues: One regards deep submicron fabrication technologies. Future semiconductor technologies could become more susceptible to alpha particles and other cosmic radiation. The other is the increasing popularity of mobile platforms. Cellular telephones are currently used for applications which are critical to our financial security, such as mobile banking, mobile trading, and making airline ticket reservations. Such applications demand that computer systems work correctly. In light of this, we propose a mechanism which is based on an instruction reissue technique for incorrect data speculation recovery and utilizes time redundancy, and evaluate our proposal using a timing simulator.

We propose an efficient algorithm for making multi-layered neural networks (MLN) fault-tolerant to all multiple weight faults in a multi-dimensional interval by injecting intentionally two extreme multi-dimensional values in the interval into the weights of the selected multiple links in a learning phase. The degree of fault-tolerance to a multiple weight fault is measured by the number of essential multiple links. First, we analytically discuss how to choose effectively the multiple links to be injected, and present a learning algorithm for making MLNs fault tolerant to all multiple (i.e., simultaneous) faults in the interval defined by two multi-dimensional extreme points. Then it is proved that after the learning algorithm successfully finishes, MLNs become fault tolerant to all multiple faults in the interval. It is also shown that the time in a weight modification cycle depends little on multiplicity of faults k for small k. These are confirmed by simulation.

In this letter, a simple peak-to-average power ratio (PAPR) reduction scheme by using a cyclic-shifted sequence mapping is addressed in OFDM-CDMA systems. The PAPR reduction approach is very simple because of no additional complexity and no side information. Also, this simple approach can be easily combined with a modified selective mapping (SLM) approach, which outperforms the original SLM approach at the expense of one additional side information, guaranteeing approximately same transmitter complexity.

The application of fault injection in the context of dependability benchmarking is far from being straightforward. One decisive issue to be addressed is to what extent injected faults are representative of the considered faults. This paper proposes an approach to analyze the effects of real and injected faults.

Space-Time Turbo code is an effective method for the enhancement of link capacity and maximizing the link-budget by balancing the coding gain obtained via Turbo codes and the diversity gain obtained through multiple antenna transmission. A study on an antenna selection scheme for Space-Time Turbo code for OFDM systems is presented in this paper. In the proposed method, the systematic bits and the punctured parity bits are sent from the selected antenna for each sub-carrier, while data transmission is suspended from the antenna experiencing poor channel conditions at the receiver. Simulation results show that the proposed method yields a 2.2 dB gain in the required TxEb/N0 relative to the conventional method, and makes the channel estimation accuracy more robust. Moreover, the proposed method reduces transmission power by about 4 dB compared to the conventional method.

For the channel estimation in the pilot channel aided CDMA systems which can support a multi-code scheme, we consider a linear prediction using both pilot and traffic channels. After deriving a new form of the optimal Wiener filter which requires less computational load, for its practical implementation, we propose the decision-directed adaptive linear prediction filter (DD-ALPF). To prevent from falling into the false lock, the proposed DD-ALPF uses the conventional channel estimate obtained only from pilot channel as a baseline for checking the reliability of the filter output. It will be shown through computer simulation that the proposed method can improve the receiver performance and performs better in the fast fading environments, compared with the existing ones.

This letter examines a very simple iterative chip-by-chip multiuser detection strategy for spread spectrum communication systems. An interleaving-based multiple-access transmission technique is employed to facilitate detection. The proposed scheme can achieve near single-user performance in situations with very large numbers of users while maintaining very low receiver complexity.

A new algorithm for fast detection and tracking of moving targets using a mobile video camera is presented. Our algorithm is based on image feature detection and matching. To detect features, we used edge points and their accumulated curvature. When the features are detected they are matched with their corresponding points using a new method called fuzzy-edge based feature matching. The proposed algorithm has two modes: detection and tracking. In the detection mode, background motion is estimated and compensated using an affine transformation. The resultant motion-rectified image is used for detection of the target location using split and merge algorithm. We also checked other features for precise detection of the target. When the target is identified, algorithm switches to the tracking mode, which also has two phases. In the first phase, the algorithm tracks the target with the intention to recover the target bounding-box more precisely and when the target bounding-box is determined precisely, the second phase of tracking algorithm starts to track the specified target more accurately. The algorithm has good performance in the environment with noise and illumination change.

In the paper we evaluate program susceptibility to hardware faults using fault injector. The performed experiments cover many applications with different features. The effectiveness of software techniques improving system dependability is analyzed. Practical aspects of embedding these techniques in real programs are discussed. They have significant impact on the final fault robustness.

A novel double-image Green's function approach is proposed to compute the frequency- dependent capacitance and conductance for the general CMOS oriented transmission lines with one protective layer. The ε-algorithm of Pade approximation is adopted to reduce the time for establishing coefficient matrix in this letter. The parameters gained from this new approach are shown to be in good agreement with the data obtained by the full-wave method and the total charge Green's function method.

By adding an auxiliary transformer to a single-stage single-switch power-factor-corrected converter (S4PFCC), the storage capacitor voltage and its range of voltage change against line voltage change are reduced. In addition, this transformer provides a direct power transfer path for input line to output load to increase the conversion efficiency. High power factor is maintained due to the elimination of dead angle of the input current. This paper presents detailed analysis and optimal design of a discontinuous conduction mode (DCM) boost-flyback S4PFCC with the auxiliary transformer. Experimental results for a 15 V/60 W prototype and with comparison to a S4PFCC without the auxiliary transformer are given to show the proposed approach effective.

This study examines a slitted parallel plate waveguide (PPW) from the perspective of diffraction and equivalent circuit representation for a narrow slit and radiation, including the surface wave effect, from a wide slit. The fundamental differences between the diffraction and equivalent admittance properties of the slit discontinuities in typical microstrip and waveguide structures are considered by comparing how the waveguide heights of the PPW and dielectric constants filling the inside of the PPW correspond to those of the two structures, respectively.

In a content-based image retrieval (CBIR) system, both the retrieval relevance and the response time are very important. This letter presents the condensed two-stage search method as a new fast image retrieval approach by making use of the property of Cauchy-Schwarz inequality. The method successfully reduces the overall processing time for similarity computation, while maintaining the same retrieval relevance as the conventional exhaustive search method. By the extensive computer simulations, we observe that the condensed two-stage search method is more effective as the number of images and dimensions of the feature space increase.

We present a new and efficient approach for extracting on-chip mutual inductances of VLSI interconnects by applying approximation formulae. The equations are based on the assumption of filaments or bars of finite width and zero thickness and are derived through Taylor's expansion of the exact formula for mutual inductance between filaments. Despite the assumption of uniform current density in each of the bars, the model is sufficiently accurate for the interconnections of current and future LSIs because the skin and proximity effects do not affect most wires. Expression of the equations in polynomial form provides a balance between accuracy and computational complexity. These equations are mapped according to the geometric structures for which they are most suitable in minimizing the runtime of inductance calculation while retaining the required accuracy. Within geometrical constraints, the wires are of arbitrary specification. Results of a comprehensive evaluation based on the ITRS-specified global wiring structure for 2003 shows that the inductance values were extracted by using the proposed approach, and they were within several percent of the values obtained by using commercial three-dimensional (3-D) field solvers. The efficiency of the proposed approach is also demonstrated by extraction from a real layout design that has 300-k interconnecting segments.

Vertical stacking is a novel technique for building switching networks, and packing multiple compatible connections together is an effective strategy to reduce network hardware cost. In this paper, we study the crosstalk-free permutation capability of an optical switching network built on the vertical stacking of optical banyan networks to which packing strategy is applied. We first look into the nonblocking condition of this optical switching network. We then study the crosstalk-free permutation in this network by decomposing a permutation evenly into multiple crosstalk-free partial permutations (CFPPs) and realizing each CFPP in a stacked plane of the network such that a crosstalk-free permutation can be performed in a single pass. We present a rigorous proof of CFPP decomposability of a permutation and also a complete algorithm for CFPP decomposition. The possibility of a tradeoff between the number of passes and the number of planes required for realizing a crosstalk-free permutation in this network is also explored in this paper.

In this paper, the absorbing property of the discrete Green's function ABC, which was based on a powerful concept of the TLM method, has been improved by relocating loss process from the time domain to the space domain. The proposed scheme simply adds a loss matrix to the connection matrix in the basic TLM algorithm to make the formulation of the ABC more efficient. Various lengths of absorbing layers discretized for a WR-90 empty waveguide have been tested in terms of reflection property. An expression for an optimum absorbing property has been also derived with respect to the length of the layer. Comparison of the layer with the discrete Green's function ABC shows that the layer in this study has improved reflection property better than approximately 3 and 6 dB, respectively, when 50Δ and 60Δ absorbing layers have been adopted for the WR-90 waveguide. Finally, the layer has been applied to a WR-75 metal insert filter as an example.

Both Cr2O3 and NiO absorb 28 GHz milli-meter-wave energy well and this strong coupling with millimeter-waves can be used to promote a chemical reaction with La2O3 to form perovskite-type LaCrO3 or LaNiO3 ceramics. In La2O3-Cr2O3 system, the reaction proceeded rapidly and single phase LaCrO3 could be synthesized within 15 min even at lower temperature (400) as compared to conventional synthesis (T > 800). In the case of LaNiO3, the reaction proceeded rapidly in the early stage of heating (t < 15 min), but not completed even after prolonged millimeter-wave irradiation. The results suggest an importance of millimeter-wave penetration depth, especially for processing of conductive materials.

Development of non-invasive techniques to measure blood sugar level is strongly required. The application of millimeter waves has a great potentiality to realize the measuring technique. Nevertheless, the practical method of the technique is not yet reported. In this paper, a new technique is proposed to measure blood sugar level using millimeter waves. The technique proposed here is very rapid and safety way to obtain blood sugar level.

This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. Experimental results for several real embedded applications, show power reduction without performance penalty range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.