The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.

The present study examined the evaluation of aging using the photic driving response, a measure used in routine EEG examinations. We examined 60 normal participants without EEG abnormalities, classified into three age groups (2029, 3059 and over 60 years; 20 participants per group). EEG was measured at rest and during photic stimulation (PS). We calculated Z-scores as a measure of enhancement and suppression due to visual stimulation at rest and during PS and tested for between-group and intraindividual differences. We examined responses in the alpha frequency and harmonic frequency ranges separately, because alpha suppression can affect harmonic frequency responses that overlap the alpha frequency band. We found a negative correlation between Z-scores for harmonics and age by fitting the data to a linear function (CC: -0.740). In contrast, Z-scores and alpha frequency were positively correlated (CC: 0.590).

Low drop-out regulators (LDOs) are widely used in the system-on-a-chip (SoC) design. Due to the multi-function and energy saving requirements for mobile applications nowadays, more strict specifications are expected on the developmental roadmap of the LDOs. An output-capacitorless LDO providing fast transient response under the low supply voltage and low quiescent current conditions is proposed in this paper. Provided by the low supply voltage, the proposed LDO adopts cascading technique using the Multipath Nested Miller Compensation (MNMC) to maintain a higher bandwidth for fast transient requirement. In addition, a Transient Quiescent Current Booster (TQCB) is supplemented to the operational amplifier to improve the slew rate for the fast load transient. The TQCB only raises the quiescent current during the load transient instant so that both power saving and the load response improvement could be well achieved. It deserves noting that the proposed TQCB contains only two transistors, which is simple to be implemented compared to the other transient current enhancement techniques. The designed LDO has only 1.6 pF capacitance for the totally added on-chip compensation, and 25.8 µA of current consumption in the main amplifier. The recovery time under the fast load change is less than 3 µs and the stability is guaranteed. Test results from the real implementation of a 0.35 µm CMOS process verify that the designed LDO performs as expected.

A semi-analytical approach for analyzing the electromagnetic radiation of a line source in cylindrical electromagnetic bandgap (EBG) structure is presented. The cylindrical structure is composed of circular rods periodically distributed along concentrically layered circular rings. The method uses the T-matrix of a circular rod in isolation, the reflection and transmission matrices of a cylindrical array expressed in terms of the cylindrical waves as the basis, and the generalized reflection and transmission matrices for a layered cylindrical structure. Using the proposed method, the radiated field from a line source placed inside a three-layered cylindrical EBG structure with defects is investigated. The defects are created by removing the particular circular rods from each circular ring. The structure is prominent from the viewpoint of flexible design of the directive antennas. Numerical examples demonstrate that the cylindrical EBG structures are very effective at forming and controlling the directed beam in the radiated fields.

In future mobile networks, the ever-increasing loads imposed by mobile Internet traffic will force the network architecture to be changed from hierarchical to flat structure. Most of the existing mobility protocols are based on a centralized mobility anchor, which will process all control and data traffic. In the flat network architecture, however, the centralized mobility scheme has some limitations, such as unwanted traffic flowing into the core network, service degradation by a single point of failure, and increased operational costs, etc. This paper proposes mobility schemes for distributed mobility control in the flat network architecture. Based on the Proxy Mobile IPv6 (PMIP), which is a well-known mobility protocol, we propose the three mobility schemes: Signal-driven PMIP (S-PMIP), Data-driven Distributed PMIP (DD-PMIP), and Signal-driven Distributed PMIP (SD-PMIP). By numerical analysis, we show that the proposed distributed mobility schemes can give better performance than the existing centralized scheme in terms of the binding update and packet delivery costs, and that SD-PMIP provides the best performance among the proposed distributed schemes.

In this paper, we propose precoding and power allocation strategies for full-duplex multiple input multiple output (MIMO) relays. The precoding scheme for full-duplex MIMO relays is derived based on the block diagonalization (BD) method to suppress the self-interference in the full-duplex relaying so that each relay station (RS) can receive multiple data streams from the base station (BS), while forwarding the decoded data streams to mobile stations (MS's) simultaneously. We also develop the optimal power allocation scheme for full-duplex MIMO relays. Numerical results verify that the proposed scheme provides substantial performance improvement compared with the conventional half-duplex relay (HDR), if sufficient physical isolation between the transmit and receive antennas is ensured such that the proposed full-duplex MIMO relays operate in a tolerable self-interference range.

Multiple-attribute based handoff schemes suffer from instability because of the dynamic nature of attributes and the distribution of handoff procedure over candidate networks, resulting in frequent handoffs that degrade the efficiency of resource management. To alleviate such instability, a service-history based scheme was proposed but it has several improper design decisions, e.g. it considers the history factors too optimistically and employs fixed weights that are likely to distort handoff decisions. This letter proposes to improve handoff performance by considering network state along with the service history. It takes into account the network utilization to avoid the optimistic dependency on the history and adaptively determines the weight to the service history in order to adjust its effect on the handoff decision. Simulation results show that the proposed scheme optimizes the number of handoff and the dropping probability when compared with existing schemes.

This paper presents a new low-dropout (LDO) regulator with low-quiescent, high-drive and fast-transient performance. This is based on a new composite power transistor composed of a shunt feedback class-AB embedded gain stage and the application of dynamic-biasing schemes to both the error amplifier as well as the composite power transistor. The proposed LDO regulator has been simulated and validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO regulator consumes 4.7 µA quiescent current at no load, regulating the output at 1 V from a minimum 1.2 V supply. It is able to deliver up to 450 mA load current with a dropout of 200 mV. It can be stabilized using a 4.7 µF output capacitor with a 0.1 Ω ESR resistor. The maximum transient output voltage is 64.6 mV on the basis of a load step change of 450 mA/10 ns under typical condition. The full load transient response is less than 350 ns.

This paper presents a content-addressable memory (CAM) using a phase-change device. A hierarchical match-line structure and a one-hot-spot block code are indispensable to suppress the resistance ratio of the phase-change device and the area overhead of match detectors. As a result, an 8-nsec 72-bit-parallel-search CAM is implemented using a phase-change-device/MOS-hybrid circuitry, where high and low resistances are higher than 2.3 MΩ and lower than 97 kΩ, respectively, while maintaining one-day retention.

A dual-band divide-by-2 quadrature injection-locked frequency divider (QILFD) is proposed to achieve high-speed, low power, wide-locking range, and accurate quadrature output phases. The QILFD consists of two dual-resonance differential voltage controlled oscillators and four coupling NMOS injectors in a ring configuration. The injectors are used as coupling devices of two differential ILFDs and are also used as common source amplifiers. The proposed QILFD has been implemented with the TSMC 90 nm CMOS technology and the core power consumption is 2.31 mW at the dc drain-source bias of 0.5 V. At the input power of 0 dBm, the low-band and high-band divide-by-2 operation ranges are respectively from 7.0 GHz to 10.1 GHz and 19.8 GHz to 24.6 GHz.

We present the recovery of 2.5 Gb/s synchronous 16-point quadrature amplitude modulation data in real-time for an linewidth-times-symbol-duration ratio of 0.00048 after transmission over 1.6 km standard single mode fiber.

We demonstrate high baud-rate DQPSK modulation with full-ETDM technique using a novel high-speed optical IQ modulator consisting of a ridge-type optical waveguide structure on a thin LiNbO3 substrate. Our fabrication technique achieves a drastic extension of the modulator's bandwidth and a reduction of half-wave voltage. Demonstration of 90-Gbaud NRZ-DP-DQPSK signal generation with the modulator successfully achieved a bit rate of 360-Gb/s under full-ETDM configuration.

We describe a concept and realization of distance-adaptive (DA) resource allocation in spectrum-sliced elastic optical path network (SLICE). We modify the modulation format and cross-connection bandwidth of individual fixed-bit rate optical paths to optimize performance with respect to transmission distance. The shorter paths are allocated a smaller amount of resources which allows reducing the spectrum occupied by the channel. We show in calculation a reduction in required spectral resources of more than 60% when compared to the traditional traffic allocation schemes based on ITU-T grid. The concept is verified experimentally.

Quadratic congruence code (QCC)-based frequency-hopping and time-spreading (FH/TS) optical orthogonal codes (OOCs), and the corresponding expanded cardinality were recently studied to improve data throughput and code capacity. In this paper, we propose a new FH/TS two-dimensional (2-D) code using the QCC and the cubic congruence code (CCC), named as the QCC/CCC 2-D code. Additionally the expanded CCC-based 2D codes are also considered. In contrast to the conventional QCC-based 1-D and QCC-based FH/TS 2-D optical codes, our analysis indicates that the code capacity of the CCC-based 1-D and CCC-based FH/TS 2-D codes can be improved with the same code weight and length, respectively.

We propose a polarization-multiplexing QPSK modulator for synthesis of a 16 QAM signal. The generation mechanism of 16 QAM is based on an electro-optic vector digital-to-analog converter, which can generate optical multilevel signals from binary electric data sequences. A quad-parallel Mach-Zehnder modulator (QPMZM) used in our previous research requires precise control of electric signals or fabrication of a variable optical attenuator, which significantly raises the degree of difficulty to control electric signals or device fabrication. To overcome this difficulty, we developed the polarization-multiplexing QPSK modulator, which improved the method of superposition of QPSK signals. In the polarization-multiplexing QPSK modulator, two QPSK signals are output with orthogonal polarization and superposed through a polarizer. The amplitude ratio between the two QPSK signals can be precisely controlled by rotating the polarizer to arrange the 16 symbols equally. Generation of 16 QAM with 40 Gb/s and a bit error rate of 5.6910-5 was successfully demonstrated using the polarization-multiplexing QPSK modulator. This modulator has simpler configuration than the previous one, utilized a dual-polarization MZM, alleviating complicated control of electric signals.

This paper introduces a hard handover strategy with a novel adaptive hysteresis adjustment that is needed to reduce handover drop rate in 3GPP long term evolution (LTE). First of all, we adopt a Hybrid handover scheme considering both the received signal strength (RSS) and the load information of the adjacent evolved Node Bs (eNBs) as a factor for deciding the target eNB. The Hybrid scheme causes the load status between the adjacent eNBs to be largely similar. Then, we propose a modified load-based adaptive hysteresis scheme to find a suitable handover hysteresis value utilizing the feature of the small load difference between the target and serving eNBs obtained from the result of the Hybrid scheme. As a result, through the proposed modified load-based adaptive hysteresis scheme, the best target cell is very well selected according to the dynamically changing communication environments. The simulation results show that the proposed scheme provides good performance in terms of handover drop rate.

Railway operators adjust timetables, and accordingly reschedule rolling stock circulation and crew duties, when the train operations are disrupted by accidents or adverse weather conditions. This paper discusses the problem of rescheduling driver assignment to freight trains after timetable adjustment has been completed. We construct a network from the disrupted situation, and model the problem as an integer programming problem with set-covering constraints combined with set-partitioning constraints. The integer program is solved by column generation in which we reduce the column generation subproblem to a shortest path problem and such paths by utilizing data parallelism. Numerical experiments using a real timetable, driver scheduling plan and major disruption data in the highest-frequency freight train operation area in Japan reveal that our method provides a quality driver rescheduling solution within 25 seconds.

In this paper, we deal with the algebraic immunity of the symmetric Boolean functions. The algebraic immunity is a property which measures the resistance against the algebraic attacks on symmetric ciphers. It is well known that the algebraic immunity of the symmetric Boolean functions is completely determined by a narrow class of annihilators with low degree which is denoted by G(n,). We study and determine the weight support of part of these functions. Basing on this, we obtain some relations between the algebraic immunity of a symmetric Boolean function and its simplified value vector. For applications, we put forward an upper bound on the number of the symmetric Boolean functions with algebraic immunity at least d and prove that the algebraic immunity of the symmetric palindromic functions is not high.

Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined.

Many factors, such as noise level in the original image and the noise-removal methods that clean the image prior to performing a vectorization, may play an important role in affecting the line detection of raster-to-vector conversion methods. In this paper, we propose an empirical performance evaluation methodology that is coupled with a robust statistical analysis method to study many factors that may affect the quality of line detection. Three factors are studied: noise level, noise-removal method, and the raster-to-vector conversion method. Eleven mechanical engineering drawings, three salt-and-pepper noise levels, six noise-removal methods, and three commercial vectorization methods were used in the experiment. The Vector Recovery Index (VRI) of the detected vectors was the criterion used for the quality of line detection. A repeated measure ANOVA analyzed the VRI scores. The statistical analysis shows that all the studied factors affected the quality of line detection. It also shows that two-way interactions between the studied factors affected line detection.