A new type of mode converter that converts TE30 to TE10 mode is proposed. As an example of the ease of fabrication, holes can be drilled at the top of a metallic waveguide and dielectric rods inserted. This converter is useful for application as a power divider or power combiner.

In this paper, we extend the conventional error-trellis construction for convolutional codes to the case where a given check matrix H(D) has a factor Dl in some column (row). In the first case, there is a possibility that the size of the state space can be reduced using shifted error-subsequences, whereas in the second case, the size of the state space can be reduced using shifted syndrome-subsequences. The construction presented in this paper is based on the adjoint-obvious realization of the corresponding syndrome former HT(D). In the case where all the columns and rows of H(D) are delay free, the proposed construction is reduced to the conventional one of Schalkwijk et al. We also show that the proposed construction can equally realize the state-space reduction shown by Ariel et al. Moreover, we clarify the difference between their construction and that of ours using examples.

We present recent progress of high-speed Mach-Zehnder modulator technologies for advanced modulation formats. Multi-level quadrature amplitude modulation signal can be synthesized by using parallel Mach-Zehnder modulators. We can generate complicated multi-level optical signals from binary data streams, where binary modulated signals are vectorially summed in optical circuits. Frequency response of each Mach-Zehnder interferometer is also very important to achieve high-speed signals. We can enhance the bandwidth of the response, with thin substrate. 87 Gbaud modulation was demonstrated with a dual-parallel Mach-Zehnder modulator.

The ITU-T J.83 Annex B is a widely adopted standard in North America for digital video and audio transmission over coaxial cable. This paper proposes a new parallel processing architecture of the parity checksum generator and syndrome generator specified in the standard for packet synchronization and error detection. The proposed parallel processing architecture removes the performance bottleneck occurring in the conventional serial processing architecture, leading to significant decrease in processing time for generating a parity checksum in transmitter and a syndrome in receiver. Implementation results show that the proposed parallel processing architecture reduces the processing time by 92% for parity checksum generation and by 81% for syndrome generation over the conventional serial processing architecture.

A compact (13.38.05.6 mm) 40 Gbit/s 1.55-µm electroabsorption (EA) modulator monolithically integrated distributed feedback (DFB) laser diode (EML) [1] module integrated with a driver IC has been developed. Its compactness was realized by employing a broadband feed-through and a bias tee which were accurately designed by 3-dimensional (3D) electromagnetic simulation. It was confirmed that the simulation results of the frequency response and the actual measurement results are corresponding well. Clear eye opening of the 40 Gbit/s optical output waveform of the fabricated EML module was observed. Degradation was not observed even when the 40 Gbit/s electrical signal was launched into the module via the flexible printed circuit (FPC).

A two-quadrant CMOS current divider using a two-variable second-order Taylor series approximation is proposed. The approximation divider is realized with a compact circuit. The simulation results indicate that the compact divider has with sufficient accuracy, small distortion, and high bandwidth for only 1.8 V supply voltage.

An integral equation approach with a new solution procedure using moment method (MoM) is applied for the computation of coupled currents on the surface of a printed dipole antenna and inside its high-permittivity three-dimensional dielectric substrate. The main purpose of this study is to validate the accuracy and reliability of the previously proposed MoM procedure by authors for the solution of a coupled volume-surface integral equations system. In continuation of the recent works of authors, a mixed-domain MoM expansion using Legendre polynomial basis function and cubic geometric modeling are adopted to solve the tensor-volume integral equation. In mixed-domain MoM, a combination of entire-domain and sub-domain basis functions, including three-dimensional Legnedre polynomial basis functions with different degrees is utilized for field expansion inside dielectric substrate. In addition, the conventional Rao-Wilton-Glisson (RWG) basis function is employed for electric current expansion over the printed structure. The accuracy of the proposed approach is verified through a comparison with the MoM solutions based on the spectral domain Green's function for infinitely large substrate and the results of FDTD method.

This paper presents two power-saving designs for Quadratic Polynomial Permutation (QPP) interleave address generator of which interleave length K is fixed and unfixed, respectively. These designs are based on our observation that the quadratic term f2x2%K of f(x) = (f1x+f2x2)%K, which is the QPP address generating function, has a short period and is symmetric within the period. Power consumption is reduced by 27.4% in the design with fixed-K and 5.4% in the design with unfixed-K on the average for various values of K, when compared with existing designs.

In this paper, we have shown a major element occupying the large portion of software communications architecture (SCA)-based software defined radio (SDR) handheld embedded system and an important feature for implementing a high speed broadband radio to an SCA waveform through a couple of experiments. First, this paper identifies the main items possessing the large portion of SCA-based SDR handheld embedded system by the experiment on the target platform which is similar to a commercial mobile handheld system. Both the world interoperabillity for microwave access (WiMAX) and high speed downlink packet access (HSDPA) waveform software packages are used as an SCA waveform application. This paper also presents the results of the relative binary size distribution of SCA software resources for looking for the major elements making an SCA-based SDR handheld embedded system heavier. As a result, when focusing on the relative weight portion of SCA core framework (CF), the SCA CF takes 16% up and others have 84% out of the whole binary size distribution of SCA software resources. The results of the experiment give us notice that the weight portion of SCA CF is minor and compatible with the overall software binary size needs of an SCA-based SDR handheld embedded system, on the other hand, the practical problem on the lightweight is in a common object request broker architecture (CORBA) and extensible markup language (XML) parser resources. Second, this paper describes an important feature for implementing a high speed broadband radio to an SCA waveform and presents the performance evaluation results of the SCA port communication on both power PC (PPC) 405 and x86 processor platforms. The PPC 405 platform, which is similar to a commercial mobile handset, takes the value of average round trip time (RTT) with a maximum of thirty six millisecond. The x86 platform, however, which is analogous to a server platform, maintains stable micro-second resolution. From our experiments, we observe that rapid SCA port communication, sufficiently less than the frame length of high-speed broadband radios, should be provided for serving those radio services in a commercial handheld system based on the SCA.

We have studied the formation of Pd-nanodots on SiO2 from ultrathin Pd films being exposed to remote hydrogen plasma at room temperature, in which parameters such as the gas pressure and input power to generate H2 plasma and the Pd film thickness were selected to get some insights into surface migration of Pd atoms induced with atomic hydrogen irradiation and resultant agglomeration with cohesive action. The areal dot density was controlled in the range from 3.4 to 6.51011 cm - 2 while the dot size distribution was changed from 7 to 1.5 in average dot height with 40% variation in full-width at half maximum. We also fabricated MOS capacitors with a Pd-nanodots floating gate and confirmed the flat-band voltage shift in capacitance-voltage characteristic due to electron injection to and emission from the dots floating gate.

In a low dropout (LDO) linear regulator whose reference voltage is supplied by a bandgap reference, double stacked diodes increase the effective junction area ratio in the bandgap reference, which significantly lowers the output spectral noise of the LDO. A low noise LDO with the area-efficient bandgap reference is implemented in 0.18 µm CMOS. An effective diode area ratio of 105 is obtained while the actual silicon area is saved by a factor of 4.77. As a result, a remarkably low output noise of 186 nV/sqrt(Hz) is achieved at 1 kHz. Moreover, the dropout voltage, line regulation, and load regulation of the LDO are measured to be 0.3 V, 0.04%/V, and 0.46%, respectively.

A lexicon-driven segmentation-recognition scheme on Bangla handwritten city-name recognition is proposed for Indian postal automation. In the proposed scheme, at first, binarization of the input document is done and then to take care of slanted handwriting of different individuals a slant correction technique is performed. Next, due to the script characteristics of Bangla, a water reservoir concept is applied to pre-segment the slant corrected city-names into possible primitive components (characters or its parts). Pre-segmented components of a city-name are then merged into possible characters to get the best city-name using the lexicon information. In order to merge these primitive components into characters and to find optimum character segmentation, dynamic programming (DP) is applied using total likelihood of the characters of a city-name as an objective function. To compute the likelihood of a character, Modified Quadratic Discriminant Function (MQDF) is used. The features used in the MQDF are mainly based on the directional features of the contour points of the components. We tested our system on 84 different Bangla city-names and 94.08% accuracy was obtained from the proposed system.

In this paper, the device performances of sub-10 nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10 nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20 nm to 4 nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10 nm generation.

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90 nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

The paper demonstrates a novel two-peak negative differential resistance (NDR) circuit combining Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Compared to the resonant-tunneling diode, MOS-HBT-NDR has two major advantages in our circuit design. One is that the fabrication of this MOS-HBT-NDR-based application can be fully implemented by the standard BiCMOS process. Another is that the peak current can be effectively adjusted by the controlled voltage. The peak-to-valley current ratio is about 4136 and 9.4 at the first and second peak respectively. It is very useful for circuit designers to consider the NDR-based applications.

How to reduce noise with less speech distortion is a challenging issue for speech enhancement. We propose a novel approach for reducing noise with the cost of less speech distortion. A noise signal can generally be considered to consist of two components, a "white-like" component with a uniform energy distribution and a "color" component with a concentrated energy distribution in some frequency bands. An approach based on noise eigenspace projections is proposed to pack the color component into a subspace, named "noise subspace". This subspace is then removed from the eigenspace to reduce the color component. For the white-like component, a conventional enhancement algorithm is adopted as a complementary processor. We tested our algorithm on a speech enhancement task using speech data from the Texas Instruments and Massachusetts Institute of Technology (TIMIT) dataset and noise data from NOISEX-92. The experimental results show that the proposed algorithm efficiently reduces noise with little speech distortion. Objective and subjective evaluations confirmed that the proposed algorithm outperformed conventional enhancement algorithms.

We propose a Solid-State Disk (SSD) with a Double Data Rate (DDR) DRAM interface for high-performance PCs. Traditional SSDs simply inherit the interface protocol of Hard Disk Drives (HDD) such as Parallel Advanced Technology Attachment (PATA) or Serial-ATA (SATA) for maintaining the compatibility. However, SSD itself provides much higher performance than HDD, hence the interface also needs to be enhanced. Unlike the traditional SSDs, the proposed SSD with DDR DRAM interface is placed in the North Bridge which provides two or more DDR DRAM interface ports in high-performance PCs. The novelty of our work is on DQS signaling scheme which allows arbitrary Column Address Strobe (CAS) latency unlike typical DDR DRAM interface scheme. The experimental results show that the proposed SSD maximally outperforms the traditional SSD by 8.7 times in read mode, by 1.5 times in write mode. Also, for synthetic workloads, the proposed scheme shows performance improvement over the conventional architecture by a factor of 1.6 times.

This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.