To deal with the increasing number of mobile devices accessing the Internet and the increasing demands of mobility management, IETF has proposed Mobile IPv6 and its fast handover protocol FMIPv6. In FMIPv6, the possibility of Care-of Address (CoA) collision and the time for Return Routability (RR) procedure result in long handover delay, which makes it unsuitable for real-time applications. In this paper, we propose an improved handover scheme for FMIPv6, which reduces the handover delay by using proactive CoA acquisition, configuration and test method. In our proposal, collision-free CoA is proactively prepared, and the time for RR procedure does not contribute to the handover delay. Furthermore, we analyze our proposal's benefits and overhead tradeoff. The numerical results demonstrate that it outperforms the current schemes, such as FMIPv6 and enhanced FMIPv6, on the aspect of handover delay and packet transmission delay.

In this letter, we develop an analytical model for the drive-thru applications based on the IEEE 802.11p WAVE. The model shows that prioritizing the bitrates via the 802.11e EDCA mechanism leads to significant throughput improvement.

In this work, we propose a scheme of routing table compaction for IP forwarding engines based on ternary content addressable memory (TCAM). Our scheme transforms the original routing table into a form with only disjoint prefixes. The most prevalent next hop of the routing table is then calculated and the route prefixes corresponding to the next hop are replaced by one TCAM entry. In combination with Espresso-II logic minimization algorithm, the proposed scheme reduces the TCAM storage requirements by more than 75% compared to the original routing tables. We also present an effective approach to support incremental updates.

A low-voltage quadrature up-conversion CMOS mixer for 5-GHz wireless communication applications is designed with a TSMC 0.18-µm process. The fold-switching technique is used to implement the low-voltage double balanced quadrature mixer. A miniature lumped-element microwave broadband rat-race hybrid and RLC shift network are used for the local oscillator and the intermediate frequency port design, respectively. The measured results demonstrate that the mixer can reach a high conversion gain, a low noise figure (NF), and a high linearity. The mixer exhibits improvement in noise, conversion gain, and image rejection. The mixer shows a conversion gain of 16 dB, a noise figure of 12.8 dB, an image rejection of 45 dB, while dissipating 15.5 mW for an operating voltage at 1 V.

According to the recent observations of IPv4 (Internet Protocol version 4) address allocation status, it will be running out within few years. Consequently, to ensure the continuous extension of the Internet operation, introducing IPv6 (Internet Protocol version 6) protocol is surely needed. But at the same time, such transformation must be "smooth" for every Internet users and be compatible with today's IPv4 based practices. This paper describes several techniques and usage scenario which are discussed mainly in the IETF -- Internet Engineering Task Force -- and tried to be implemented as prototype products to transform today's Internet towards the IPv6 based one.

With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and Ileakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

In this letter, a novel technique for fast block matching using a new matching criterion is proposed. The matching speed and image quality are controlled by the one control parameter called matching region ratio. An efficient matching scheme with a gradual voting strategy is also proposed. This scheme can greatly boost the matching speed. The proposed technique is fast and applicable even in the presence of speckle noise or partial occlusion.

This letter proposes a fast IP address lookup algorithm based on search space reduction. Prefixes are classified into three types according to the nesting relationship and a large forwarding table is partitioned into multiple small trees. As a result, the search space is reduced. The results of analyses and experiments show that the proposed method offers higher lookup and updating speeds along with reduced memory requirements.

This paper presents a real integration of a 5.8-GHz injection-locked quadrature local oscillator that includes two LC-tuned injection-locked frequency dividers (ILFDs) and a wide-tuning stacked-transformer feedback voltage-controlled oscillator (VCO) operated in double frequency. A symmetric differential stacked-transformer with a high coupling factor and a high quality factor is used as a feedback component for the wide-tuning VCO design. The wide tuning range, which is greater than three times the desired bandwidth, is achieved by selecting a greater tuning capacitance ratio available from high-voltage N-type accumulation-mode MOS varactors and a smaller self-inductance stacked-transformer. Since the quality factors of the LC-resonator components can sustain at a high enough level, the wide-tuning VCO does not suffer from the phase noise degradation too much. In addition, the tuning range of the local oscillator is extended simultaneously by utilizing switched capacitor arrays (SCAs) in the ILFDs. The circuit is implemented by TSMC's 0.18-µm RF CMOS technology. At a 1-V power supply, the whole integrated circuit dissipates 6.72 mW (4.05 mW for the VCO and 2.67 mW for the two ILFDs). The total tuning range frequency is about 500 MHz (from 5.54 GHz to 6.04 GHz) when the tuning voltage Vtune ranges from 0 V to 1.8 V. At around the output frequency of 5.77 GHz (at Vtune = 0.5 V), the measured phase noise of this local oscillator is -119.4 dBc/Hz at a 1-MHz offset frequency. This work satisfies the specification requirement for IEEE 802.11a UNII-3 band application. The corresponding figure-of-merit (FOM) calculated is 186.3 dB.

It is a well-known fact that the BMS algorithm with majority voting can decode up to half the Feng-Rao designed distance dFR. Since dFR is not smaller than the Goppa designed distance dG, that algorithm can correct up to errors. On the other hand, it has been considered to be evident that the original BMS algorithm (without voting) can correct up to errors similarly to the basic algorithm by Skorobogatov-Vladut. But, is it true? In this short paper, we show that it is true, although we need a few remarks and some additional procedures for determining the Groebner basis of the error locator ideal exactly. In fact, as the basic algorithm gives a set of polynomials whose zero set contains the error locators as a subset, it cannot always give the exact error locators, unless the syndrome equation is solved to find the error values in addition.

A time-slicing ring oscillator (TSRO) which captures time-dependent delay degradation due to periodic transient voltage drop on a power supply network is proposed. An impact of the supply voltage fluctuations, including voltage drop and overshoot, on logic circuit delay is evaluated as a change of oscillation frequency. The TSRO is designed using standard logic cells so that it can be placed almost anywhere in a digital circuit wherein supply voltage fluctuation is concerned. We also propose a new procedure for reconstructing supply voltage waveform. The procedure enables us to accurately monitor time-dependent, effective supply voltages. The -1 dB bandwidth of the TSRO is simulated to be 15.7 GHz, and measured time resolution is 131 ps. Measurement results of a test chip using 90-nm standard CMOS process successfully proved the feasibility of both delay degradation and effective supply voltage fluctuation measurements. Measurement of spatial voltage drop fluctuation is achieved.

The National Institute of Information and Communications Technology (NICT) vision and five network targets of research and development (R&D) of the NeW-Generation Network (NWGN) are presented in this letter. The NWGN is based on new design concepts that look beyond the next generation network (NGN). The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by using information and communication technologies (ICTs). NICT's vision for NWGN is also presented in this letter. Based on this vision, 19 items concerning social issues and future social outlook are analyzed, and the functional requirements of the NWGN are extracted. The requirements are refined and categorized into five network targets that must be developed for realizing the vision.

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, Δ Vt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5 V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for ΔVt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5 V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

The current Internet is not capable of meeting the future communication requirements of society, i.e., reliable connectivity in a ubiquitous networking environment. The shortcomings of the Internet are due to the lack of support for mobility, multihoming, security and heterogeneous network layer protocols in the original design. Therefore, to provide ubiquitous networking facilities to the society for future innovation, we have to redesign the future Internet, which we call the New Generation Network. In this paper, we present the Heterogeneity Inclusion and Mobility Adaptation through Locator ID Separation (HIMALIS) architecture for the New Generation Network. The HIMALIS architecture includes a new naming scheme for generating host names and IDs. It also includes a logical control network to store and distribute bindings between host names, IDs, locators and other information useful for providing support for network operation and control. The architecture uses such information to manage network dynamism (i.e., mobility, multihoming) and heterogeneity in network layer protocols. We verify the basic functions of the architecture by implementing and testing them using a testbed system.

It is well known that the performance of turbo codes can be improved by optimizing the energy allocation on coded symbols. Based on this fact, we propose an optimized 16-quadrature amplitude modulation (QAM) constellation for binary turbo codes. In the proposed scheme, the energy allocated on turbo coded symbols is optimized by modifying the constellation of QAM. The proposed 16-QAM constellation combined with a binary turbo code offers better coding gain compared to the conventional combination of binary turbo code and QAM.

Unlike the conventional plasma-TVs using the driving circuit with two polarities during the reset and address periods, the cost-effective driving circuit using only the positive voltage level during the reset and address periods is proposed and implemented in the 42-in. plasma-TV.

We propose a surface profiling algorithm by white-light interferometry that extends sampling interval to twice of the widest interval among those used in conventional algorithms. The proposed algorithm uses a novel function called an in-phase component of an interferogram to detect the peak of the interferogram, while conventional algorithms used the squared-envelope function or the envelope function. We show that the in-phase component has the same peak as the corresponding interferogram when an optical filter has a symmetric spectral distribution. We further show that the in-phase component can be reconstructed from sampled values of the interferogram using the so-called quadrature sampling technique. Since reconstruction formulas used in the algorithm are very simple, the proposed algorithm requires low computational costs. Simulation results show the effectiveness of the proposed algorithm.

This paper is concerned with the estimation of radio communication distance when both the transmitter and receiver are arbitrarily distributed on a random rough surface such as desert, terrain, sea surface and so on. First, we simulate electromagnetic wave propagation along the rough surface by using the discrete ray tracing method (DRTM) proposed by authors recently. Second, we determine three parameters by conjugate gradient method (CGM) combined with the method of least-squares. Finally, we derive an analytical expression which can estimate the maximum communication distance when the input power of a transmitter and the minimum detectable electric intensity of a receiver are specified. Random rough surfaces are assumed to be Gaussian, pn-th order power law or exponential distributions.

In this paper, we propose a Modified nested sparse grid based Adaptive Stochastic Collocation Method (MASCM) for block-based Statistical Static Timing Analysis (SSTA). The proposed MASCM employs an improved adaptive strategy derived from the existing Adaptive Stochastic Collocation Method (ASCM) to approximate the key operator MAX during timing analysis. In contrast to ASCM which uses non-nested sparse grid and tensor product quadratures to approximate the MAX operator for weakly and strongly nonlinear conditions respectively, MASCM proposes a modified nested sparse grid quadrature to approximate the MAX operator for both weakly and strongly nonlinear conditions. In the modified nested sparse grid quadrature, we firstly construct the second order quadrature points based on extended Gauss-Hermite quadrature and nested sparse grid technique, and then discard those quadrature points that do not contribute significantly to the computation accuracy to enhance the efficiency of the MAX approximation. Compared with the non-nested sparse grid quadrature, the proposed modified nested sparse grid quadrature not only employs much fewer collocation points, but also offers much higher accuracy. Compared with the tensor product quadrature, the modified nested sparse grid quadrature greatly reduced the computational cost, while still maintains sufficient accuracy for the MAX operator approximation. As a result, the proposed MASCM provides comparable accuracy while remarkably reduces the computational cost compared with ASCM. The numerical results show that with comparable accuracy MASCM has 50% reduction in run time compared with ASCM.

High Dynamic Range Imaging (HDRI) refers to a set of techniques that can represent a dynamic range of real world luminance. Hence, the HDR image can be used to measure the reflectance property of materials. In order to reproduce the original color of materials using this HDR image, characterization of HDR imaging is needed. In this study, we propose a new HDRI characterization method under a known illumination condition at the HDR level. The proposed method normalizes the HDR image by using the HDR image of a light and balances the tone using the reference of the color chart. We demonstrate that our method outperforms the previous method at the LDR level by the average color difference and BRDF rendering result. The proposed method gives a much better reproduction of the original color of a given material.