A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-VT PMOS amplifier and a low-VT NMOS amplifier which is composed of high-VT NMOSs and a low-VT cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-VT CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.

A new approach to speech feature estimation under noise circumstances is proposed in this paper. It is used in noise-robust continuous speech recognition (CSR). As the noise robust techniques in isolated word speech recognition, the running spectrum analysis (RSA), the running spectrum filtering (RSF) and the dynamic range adjustment (DRA) methods have been developed. Among them, only RSA has been applied to a CSR system. This paper proposes an extended DRA for a noise-robust CSR system. In the stage of speech recognition, a continuous speech waveform is automatically assigned to a block defined by a short time length. The extended DRA is applied to these estimated blocks. The average recognition rate of the proposed method has been improved under several different noise conditions. As a result, the recognition rates are improved up to 15% in various noises with 10 dB SNR.

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

In this paper, we have proposed a new method of observing walking traces, which can observe people's indoor movement for life-logging. Particularly emphasized new techniques in this paper are methods to detect locations, where walking directions are changed, by analyzing azimuth orientations measured by an orientation sensor of an Android mobile device, and to decide walking traces by a map matching with a vector map. The experimental evaluation has shown that the proposed method can determine the correct paths of walking traces.

A new sustain driving circuit, featuring an energy-recovering function with simple structure and minimal component count, is proposed as a cost-effective solution for driving plasma display panels during the sustaining period. Compared with existing solutions, the proposed circuit reduces the number of semiconductor switches and reactive circuit components without compromising the circuit performance and gas-discharging characteristics. In addition, the proposed circuit utilizes the harness wire as an inductive circuit component, thereby further simplifying the circuit structure. The performance of the proposed circuit is confirmed with a 42-inch plasma display panel.

This paper presents the iterative progressive numerical methods (IPNMs) based on the induced dimension reduction (IDR) theorem. The IDR theorem is mainly utilized for the development of new nonstationary linear iterative solvers. On the other hand, the use of the IDR theorem enables to revise the classical linear iterative solvers like the Jacobi, the Gauss-Seidel (GS), the relaxed Jacobi, the successive overrelaxation (SOR), and the symmetric SOR (SSOR) methods. The new IPNMs are based on the revised solvers because the original one is similar to the Jacobi method. In the new IPNMs, namely the IDR-based IPNMs, we repeatedly solve linear systems of equations by using a nonstationary linear iterative solver. An initial guess and a stopping criterion are discussed in order to realize a fast computation. We treat electromagnetic wave scattering from 27 perfectly electric conducting spheres and reports comparatively the performance of the IDR-based IPNMs. However, the IDR-based SOR- and the IDR-based SSOR-type IPNMs are not subject to the above numerical test in this paper because of the problem with an optimal relaxation parameter. The performance evaluation reveals that the IDR-based IPNMs are better than the conventional ones in terms of the net computation time and the application range for the distance between objects. The IDR-based GS-type IPNM is the best among the conventional and the IDR-based IPNMs and converges 5 times faster than a standard computation by way of the boundary element method.

ITS (Intelligent Transport Systems) wireless communications system has been developing based on the leading edge ICT (Information Communication Technologies) in Japan. The comfort driving systems for example VICS (Vehicular Information Communication system), ETC (Electronic Toll Collection), Telematics has already become popular and the safety driving support systems, such as ASV (Advanced Safety Vehicle) and SMARTWAY have been scheduled for introduction in the near future. However, there are many residual issues in the comfort driving system because of the existence of the traffic jam and the interest of the economical cars in the world. Moreover, the acceleration of the development of the Smart Grid and EV (Electric Vehicle) would affect the future development of the ITS wireless communications system. In this paper, it is clarified that the future development should be advanced considering the one of the basic business rule of 'market-in and product-out'.

Based on quadriphase perfect sequences and their cyclical shift versions, three families of almost perfect 16-QAM sequences are presented. When one of two time shifts chosen equals half a period of quadriphase sequence employed and another is zero, two of the proposed three sequence families possess the property that their out-of-phase autocorrelation function values vanish except one. At the same time, to the other time shifts, the nontrivial autocorrelation function values in three families are zero except two or four. In addition, two classes of periodic complementary sequence (PCS) pairs over the 16-QAM constellation, whose autocorrelation is similar to the one of conventional PCS pairs, are constructed as well.

Permutation polynomial based interleavers over integer rings have recently received attention for their excellent channel coding performance, elegant algebraic properties and simplicity of implementation. In this letter, it is shown that permutation polynomial based interleavers of practical interest is decomposed into linear permutation polynomials. Based on this observation, it is shown that permutation polynomial based interleavers as well as their inverses can be efficiently implemented.

In this letter, we propose a novel speech enhancement algorithm based on data-driven residual gain estimation. The entire system consists of two stages. At the first stage, a conventional speech enhancement algorithm enhances the input signal while estimating several signal-to-noise ratio (SNR)-related parameters. The residual gain, which is estimated by a data-driven method, is applied to further enhance the signal at the second stage. A number of experimental results show that the proposed speech enhancement algorithm outperforms the conventional speech enhancement technique based on soft decision and the data-driven approach using SNR grid look-up table.

Polymer multimode optical waveguides were fabricated from optically-sensitive hybrid silicone using the ultraviolet laser drawing method. The waveguide loss values were measured as 0.069 dB/cm with a laser diode, 0.069 dB/cm with a vertical-cavity surface-emitting laser, and 0.128 dB/cm with a light-emitting diode. The cross waveguide on a curved waveguide was drawn by overlapped direct laser drawing. The crosstalk and excess loss at the cross angle of 50 in the cross waveguide were measured as 47 dB and 0.5 dB, respectively.

Dielectric rod arrays in a metallic waveguide alter the propagation modes and group velocities of electromagnetic waves. We have focused on TE30-to-TE10 mode converters and investigated how their behavior varies with frequency. A mode converter is proposed that passes the TE10 mode at frequencies lower than 2fc, and converts the TE30 mode into the TE10 mode for frequencies higher than 3fc.

In processing stream data, time is one of the most significant facts not only because the size of data is dramatically increased but because the characteristics of data is varying over time. To learn stream data evolving over time effectively, it is required to detect the drift of concept. We present a window adaptation function on domain value (WAV) to determine the size of windowed batch for learning algorithms of stream data and a method to detect the change of data characteristics with a criterion function utilizing correlation. When applying our adaptation function to a clustering task on a multi-stream data model, the result of learning synopsis of windowed batch determined by it shows its effectiveness. Our criterion function with correlation information of value distribution over time can be the reasonable threshold to detect the change between windowed batches.

Although IP address lookup schemes using ternary content addressable memory (TCAM) can perform high speed packet forwarding, TCAM is much more expensive than ordinary memory in implementation cost. As a low-cost solution, binary search algorithms such as a binary trie or a binary search tree have been widely studied. This paper proposes an efficient IP address lookup scheme using balanced binary search with minimal entries and optimal prefix vectors. In the previous scheme with prefix vectors, there were numerous pairs of nearly identical entries with duplicated prefix vectors. In our scheme, these overlapping entries are combined, thereby minimizing entries and eliminating the unnecessary prefix vectors. As a result, the small balanced binary search tree can be constructed and used for a software-based address lookup in small-sized routers. The performance evaluation results show that the proposed scheme offers faster lookup speeds along with reduced memory requirements.

High Dynamic Range (HDR) images have been widely applied in daily applications. However, HDR image is a special format, which needs to be pre-processed known as tone mapping operators for display. Since the visual quality of HDR images is very sensitive to luminance value variations, conventional watermarking methods for low dynamic range (LDR) images are not suitable and may even cause catastrophic visible distortion. Currently, few methods for HDR image watermarking are proposed. In this paper, two watermarking schemes targeting HDR images are proposed, which are based on µ-Law and bilateral filtering, respectively. Both of the subjective and objective qualities of watermarked images are greatly improved by the two methods. What's more, these proposed methods also show higher robustness against tone mapping operations.

A reliable antifuse scheme has been very hard to build, which has precluded its implementation in DRAM products. We devised a very reliable multi-cell structure to cope with the large process variation in the DRAM-cell-capacitor type antifuse system. The programming current did not rise above 564 µA even in the nine-cell case. The cumulative distribution of the successful rupture in the multi-cell structure could be curtailed dramatically to less than 15% of the single-cell's case and the recovery problem of programmed cells after the thermal stress (300) had disappeared. In addition, we also presented a Post-Package Repair (PPR) scheme that could be directly coupled to the external high-voltage power rail via an additional pin with small protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1 Gbit DDR SDRAM was fabricated using Samsung's advanced 50 nm DRAM technology, successfully proving the feasibility of the proposed antifuse system implemented in it.

This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 µm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4 MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

An analysis and design of a CMOS differential pair and a common source amplifier for shaping a triangular signal into 0-π/4 segments of sine and cosine waveforms are presented. By multiplexing these two shaped outputs, low distortion full sine and cosine signals can be produced at one fourth the frequency of the triangular input. These two circuits can be combined with one DAC and a phase accumulator to form a compact quadrature direct digital frequency synthesizer (Q-DDFS) suitable for generating low distortion sinusoidal signals at low frequency. The shapers are biased by two current generators specially designed to compensate for process parameter variations. MOS dimensional mismatch is also studied. The analog part of the Q-DDFS is synthesized using 0.18-micron n-well CMOS technology. A simulation shows that the circuit consumes 1.3 mW and can generate 19.96 mV 50 kHz sine and cosine signals with spurious free dynamic range (SFDR) of around 50 dBc from a Q-DDFS running at 1.6 MHz.