The distribution of streaming multicast and real time audio/video applications in the Internet has been quickly increased in the Internet. Commonly, these applications rarely use congestion control and do not fairly share provided network capacity with TCP-based applications such as HTTP, FTP and emails. Therefore, Internet communities will be threatened by the increase of non-TCP-based applications that likely cause a significant increase of traffics congestion and starvation. This paper proposes a set of mechanisms, such as providing various data rates, background traffics, and various scenarios, to act friendly with TCP when sending multicast traffics. By using 8 scenarios of simulations, we use 6 layered multicast transmissions with background traffic Pareto with the shape factor 1.5 to evaluate performance metrics such as throughput, delay/latency, jitter, TCP friendliness, packet loss ratio, and convergence time. Our study shows that non TCP traffics behave fairly and respectful of the co-existent TCP-based applications that run on shared link transmissions even with background traffic. Another result shows that the simulation has low values on throughput, vary in jitter (0-10 ms), and packet loss ratio > 3%. It was also difficult to reach convergence time quickly when involving only non TCP traffics.

Ternary Content Addressable Memory (TCAM) is a special type of memory used in routers to achieve high-speed packet forwarding and classification. Packet forwarding is done by referring to the rules written in the routing table, whereas packet classification is performed by referring to the rules in the Access Control List (ACL). TCAM uses more transistors than Random Access Memory (RAM), resulting in high power consumption and high production cost. Therefore, it is necessary to reduce the entries written in the TCAM to reduce the transistor count. In this paper, we propose a new TCAM architecture by using Range Matching Devices (RMD) integrated within the TCAM's control logic with an optimized prefix expansion algorithm. The proposed method reduces the number of entries required to express ACL rules, especially when specifying port ranges. With less than 10 RMDs, the total number of lines required to write port ranges in the TCAM can be reduced to approximately 50%.

The purpose of this study is to establish a whole-body averaged specific absorption rate (WB-SAR) estimation method using the power absorbed by humans; a cylindrical-external field scanning technique is used to measure the radiated RF (radio-frequency) power. This technique is adopted with the goal of simplifying the estimation of the exposure dosimetry of humans who have different postures and/or sizes. In this paper, to validate the proposed measurement method, we subject numerical human phantom models and cylindrical scanning conditions to FDTD analysis. We design a radiation system that uses a dielectric lens to achieve plane-wave irradiation of tested human phantoms in order to develop an experimental WB-SAR measurement system for UHF far-field exposure condition. In addition, we use a constructed SAR measurement system to confirm absorbed power estimations of simple geometrical phantoms and so estimate measurement error of the measurement system. Finally, we discuss the measurement results of WB-SARs for male adult and child human phantom models.

This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.

Effects of atomic hydrogen annealing (AHA) on the film properties and the electrical characteristics of pentacene organic thin-film transistors (OTFTs) are investigated. The surface energy of SiO2 surface and grain size of pentacene film were decreased with increasing AHA treatment time. For the treatment time of 300 s, pentacene film showed the (00l) and (011') orientation and high carrier mobility in spite of small crystal grain.

This article presents a unified analytical framework to evaluate the bit error probability (BEP) of M-QAM, R-QAM and M-PAM modulation schemes for different types of fading channels, modeled with Hoyt, Rice, Rayleigh, Nakagami and Log-normal distributions. The mathematical development is obtained for maximal-ratio combining multichannel reception and assumes independent fading paths. The new BEP expressions are written in terms of the integral of the moment generating funcion of the instantaneos signal-to-noise ratio. The advantage of this approach is that it can be applied to any type of fading, and the integrals, even though they do not provide exact expressions, can be numerically evaluated.

The hybrid antenna consisted of cylindrical dielectric resonator and rectangular slot was implemented. The hybrid antenna resonated at two different frequencies. The lower resonant frequency was associated with the rectangular slot while the higher resonant frequency was associated with the cylindrical dielectric resonator. Parametric investigation was carried out using simulation software. The proposed hybrid antenna had good agreement between the simulation and measurement results. A 24% bandwidth (return loss < 10 dB) of 2.30 GHz, and a 18% bandwidth (return loss < 10 dB) of 5.46 GHz was implemented successfully for application in ISM and UNII band.

This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.

In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.

In an early design stage of LSI designing, finding out the proper parameters for power planning is important from the viewpoint of cost minimization. In this paper, we present simple analytical formulas which are used to obtain the initial parameters close to the proper power distribution networks in the early design stage. The formulas for estimating static and pseudo-dynamic voltage drops (IR-drops) are derived by the response surface method (RSM). By making the formulas once, they can be used for the general power planning for the power-grid style in any process technology.

In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.

This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.

This paper presents a novel noise-robust feature extraction method for speech recognition. It is based on making the Minimum Variance Distortionless Response (MVDR) power spectrum estimation method robust against noise. This robustness is obtained by modifying the distortionless constraint of the MVDR spectral estimation method via weighting the sub-band power spectrum values based on the sub-band signal to noise ratios. The optimum weighting is obtained by employing the experimental findings of psychoacoustics. According to our experiments, this technique is successful in modifying the power spectrum of speech signals and making it robust against noise. The above method, when evaluated on Aurora 2 task for recognition purposes, outperformed both the MFCC features as the baseline and the MVDR-based features in different noisy conditions.

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 38402160@60 fps decoding at less than 133 MHz, with 37.2 k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 44 block to DRAM.

A monolithic modulator driver IC based on InP HBTs with a new circuit topology -- called a functional distributed circuit (FDC) -- for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2:1 multiplexing function produces 2.6-Vp-p (differential output: 5.2 Vp-p) and 2.4- Vp-p (differential output: 4.8 Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80 Gb/s and 90 Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90 Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

10G-EPON systems have attracted a great deal of attention as a way of exceeding to realize over 10 Gb/s for optical subscriber networking. Rapid burst-mode transmitting/receiving techniques are the key technologies enabling the burst-mode upstream transmission of 10G-EPON systems. In this paper, we have developed a OLT burst-mode 3R receiver incorporating a burst-mode AGC optical receiver and an 82.5 GS/s over-sampling burst-mode CDR and a ONU burst-mode transmitter with high launch power DFB-LD of 1.27 µm wavelength to fully compliant with IEEE802.3av 10G-EPON PR30 standards. The transmitting characteristics of a fast LD turn-on/off time of less than 6ns and a high launch power of more than +8.0 dBm, and the receiving characteristics of receiver sensitivity of -30.1 dBm and the upstream power budget of 38.1 dB are successfully achieved.

In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.

We present a full description of a polarization-independent athermal differential quadrature phase shift keying (DQPSK) demodulator that employs silica-based planar lightwave circuit (PLC) technology. Silica-based PLC DQPSK demodulator has good characteristics including low polarization dependence, mass producibility, etc. However delay line interferometer (DLI) of demodulator had the large temperature dependence of its optical characteristics, so it required large power consumption to stabilize the chip temperature by the thermo-electric cooler (TEC). We previously made a quick report about an athermal DLI to reduce a power consumption by removing the TEC. In this paper, we focus on the details of the design and the fabrication method we used to achieve the athermal characteristics, and we describe the thermal stability of the signal demodulation and the reliability of our demodulator. We described two athermalization methods; the athermalization of the transmission spectrum and the athermalization of the polarization property. These methods were successfully demonstrated with keeping a high extinction ratio and a small footprint by introducing a novel interwoven DLI configuration. This configuration can also limit the degradation of the polarization dependent phase shift (PDf) to less than 1/10 that with the conventional configuration when the phase shifters on the waveguide are driven. We used our demodulator and examined its demodulation performance for a 43 Gbit/s DQPSK signal. We also verified its long-term reliability and thermal stability against the rapid temperature change. As a result, we confirmed that our athermal demodulator performed sufficiently well for use in DQPSK systems.

Hypergraphs drawn in the subset standard are useful to represent group relationships using topographic characteristics such as intersection, exclusion and enclosing. However, they present cluttering when dealing with a moderately high number of nodes (more than 20) and large hyperedges (connecting more than 10 nodes, with three or more overlapping nodes). At this complexity level, a study of the visual encoding of hypergraphs is required in order to reduce cluttering and increase the understanding of larger sets. Here we present a graph model and a visual design that help in the visualization of group relationships represented by hypergraphs. This is done by the use of superimposed visualization layers with different abstraction levels and the help of interaction and navigation through the display.

A new estimation algorithm of clock drift in symbol duration for high precision ranging, based on multiple symbols of chirp spread spectrum (CSS) is proposed. Since the permissible error of a crystal oscillator in CSS is relatively high given the need to lower device costs, ranging results are perturbed by clock drift. We establish the phenomenon of clock drift in multiple symbols of CSS, and estimate the clock drift in symbol duration based on phase difference between adjacent symbols. The proposed algorithm is analyzed, and verified by Monte Carlo simulations.