This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

In many engineering problems it is required to convert a polynomial into another polynomial through a transformation. Due to its wide range of applications, the polynomial transformation has received much attention and many techniques have been developed to compute the coefficients of a transformed polynomial from those of an original polynomial. In this letter a new result is presented concerning the transformation matrix for arbitrary polynomial transformation. A simple algorithm is obtained which enables one to successively compute transformation matrices of various order.

It is essential, as bandwidths of wireless communications get wider, to evaluate the imbalances among quadrature mixer ports, in terms of carrier phase offset, IQ gain imbalance, and IQ skew. Because it is time consuming to separate skew, gain imbalance and carrier phase offset evaluation during test is often performed using a composite value, without separation of the imbalance factors. This paper describes an algorithm for enabling separation among quadrature mixer gain imbalance, carrier phase offset, and skew. Since the test time is reduced by the proposed method, it can be applied during high volume production testing.

Noise removal in engineering drawing is an important operation performed before other image analysis tasks. Many algorithms have been developed to remove salt-and-pepper noise from document images. Cleaning algorithms should remove noise while keeping the real part of the image unchanged. Some algorithms have disadvantages in cleaning operation that leads to removing of weak features such as short thin lines. Others leave the image with hairy noise attached to image objects. In this article a noise removal procedure called TrackAndMayDel (TAMD) is developed to enhance the noise removal of salt-and-pepper noise in binary images of engineering drawings. The procedure could be integrated with third party algorithms' logic to enhance their ability to remove noise by investigating the structure of pixels that are part of weak features. It can be integrated with other algorithms as a post-processing step to remove noise remaining in the image such as hairy noise attached with graphical elements. An algorithm is proposed by incorporating TAMD in a third party algorithm. Real scanned images from GREC'03 contest are used in the experiment. The images are corrupted by salt-and-pepper noise at 10%, 15%, and 20% levels. An objective performance measure that correlates with human vision as well as MSE and PSNR are used in this experiment. Performance evaluation of the introduced algorithm shows better-quality images compared to other algorithms.

A subdivision of a rectangle into rectangular faces with horizontal and vertical line segments is called a rectangular drawing or floorplan. It has been an open problem to determine whether there exist a polynomial time algorithm for computing R(n). We affirmatively solve the problem, that is, we introduce an O(n4)-time and O(n3)-space algorithm for R(n). The algorithm is based on a recurrence for R(n), which is the main result of the paper. We also implement our algorithm and computed R(n) for n 3000.

In this paper, for odd n and any k with gcd(n,k) = 1, new binary sequence families Sk of period 2n-1 are constructed. These families have maximum correlation , family size 22n+2n+1 and maximum linear span . The correlation distribution of Sk is completely determined as well. Compared with the modified Gold codes with the same family size, the proposed families have the same period and correlation properties, but larger linear span. As good candidates with low correlation and large family size, the new families contain the Gold sequences and the Gold-like sequences. Furthermore, Sk includes a subfamily which has the same period, correlation distribution, family size and linear span as the family So(2) recently constructed by Yu and Gong. In particular, when k=1, is exactly So(2).

A trihedral corner reflector is often used for SAR polarimetric calibration. However, the scattering property of the reflector used for the calibration may not be correct if the high frequency approximation is not satisfied or if an incident angle deviates from the symmetric axis of the reflector. In order to know the conditions for precise SAR polarimetric calibration, we evaluated the polarimetric response of the reflector by a numerical simulation using the method of moment (MoM). It is found that allowable incident angle deviation is 5 degree to azimuth direction and 4 degree to elevation direction for precise SAR polarimetric calibration when the size of the reflector is 7.5 times larger than the wavelength of an incident wave.

In this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.

A novel CMOS LC quadrature oscillator (QO) which adopts complementary-coupling circuitry has been proposed. The performance improvement in I/Q phase error and phase noise of the proposed QO, is explained in comparison with conventional QOs. The proposed QO is implemented in 0.18 µm CMOS technology along with conventional QOs. The measurement result of the proposed QO shows -133.5 dBc/Hz of phase noise at 1 MHz offset and 0.6 I/Q phase difference, while oscillating at 1.77 GHz. The proposed QO shows more than 6.5 dB phase noise improvement compared to that of the conventional QOs over the offset frequency range of 10 K-1 MHz, while dissipating 4 mA from 1.4 V supply.

Because network diagrams drawn using the spring embedder are not easy to read, this paper proposes the use of "anchored maps" in which some nodes are fixed as anchors. The readability of network diagrams is discussed, anchored maps are proposed, and a method for drawing anchored maps is explained. The method uses indices to decide the orders of anchors because those orders markedly affect the readability of the network diagrams. Examples showing the effectiveness of the anchored maps are also shown.

The Letter deals with constant false alarm rate (CFAR) detection of random Gaussian target signals embedded in Gaussian clutter with unknown covariance. The proposed detector is analyzed on the assumption that clutter covariance is not known and a random target signal has low-rank property. The low-dimensional subspace-based approach leads to a robust false alarm rate (RFAR) detector. The detection performance loss and the false alarm stability loss to unknown clutter covariance have been evaluated for example scenario.

A (k,2)-track layout of a graph G consists of a 2-track assignment of G and an edge k-coloring of G with no monochromatic X-crossing. This paper studies the problem of (k,2)-track layout of bipartite graph subdivisions. Recently V. Dujmovi and D.R. Wood showed that for every integer d ≥ 2, every graph G with n vertices has a (d+1,2)-track layout of a subdivision of G with 4 log d qn(G) +3 division vertices per edge, where qn(G) is the queue number of G. This paper improves their result for the case of bipartite graphs, and shows that for every integer d ≥ 2, every bipartite graph Gm,n has a (d+1,2)-track layout of a subdivision of Gm,n with 2 log d n -1 division vertices per edge, where m and n are numbers of vertices of the partite sets of Gm,n with m ≥ n.

Harmonic balance (HB) method is well known principle for analyzing periodic oscillations on nonlinear networks and systems. Because the HB method has a truncation error, approximated solutions have been guaranteed by error bounds. However, its numerical computation is very time-consuming compared with solving the HB equation. This paper proposes an algebraic representation of the error bound using Grobner base. The algebraic representation enables to decrease the computational cost of the error bound considerably. Moreover, using singular points of the algebraic representation, we can obtain accurate break points of the error bound by collisions.

A rectangular drawing is a plane drawing in which every face is a rectangle. In this paper we give a simple encoding scheme for rectangular drawings. Given a rectangular drawing R with maximum degree 3, our scheme encodes R with m + o(n) bits where n is the number of vertices of R and m is the number of edges of R. Also we give an algorithm to supports a rich set of queries, including adjacency and degree queries on the faces, in constant time.

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gate-source and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2 µm standard CMOS technology, and a wide range of operation between 1 nW and 100 µW was demonstrated. The accuracy of the voltage follower was 30 mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10 mV. The temperature dependence of the output was 0.11 mV/. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10 mV accuracy and the cell size is 105.3µm 81.4 µm in 1.2 µm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2 mV in a range of total current between 3 nA and 10 µA and in a temperature range between 30 and 100.

A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry characteristics of IDsat and IBmax with respect to the interchange of source and drain was examined. Although both IDsat and IBmax have similar channel orientation dependence, IBmax in interchanged S/D measurements shows asymmetrical characteristics, which can be applied to a sensitive method for device asymmetry detection.

Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

An all-optical phase multiplexing scheme for phase-modulated signals is proposed and experimentally demonstrated using four-wave mixing (FWM) in a highly-nonlinear fiber (HNLF). Two 10-Gb/s π/2-shifted differential phase-shift keying (DPSK) wavelength-division multiplexing (WDM) signals are experimentally demonstrated to be converted and phase-multiplexed into a 20-Gb/s differential quadrature phase-shift keying (DQPSK) signal with non-return-to-zero (NRZ) and return-to-zero (RZ) formats, respectively. Experimental results show that, due to phase-modulation-depth doubling effect and phase multiplexing effect in the FWM process, a DQPSK signal is successfully generated through the proposed all-optical phase multiplexing with improved receiver sensitivity and spectral efficiency.

This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduling approach achieved 47.7-99.9% less vulnerability than a conventional one.