A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

This paper is concerned with the controller synthesis for feedback systems with saturation based on the LPV system representation. The LPV system representation, combined with use of the detailed structure of saturation nonlinearity, enables us to reduce the conservativeness. In this paper, we develop a new iterative algorithm for designing a linear time-invariant controller which locally stabilizes the nonlinear closed-loop system and achieves the prescribed quadratic control performance. The present design method provides an explicit expression for a guaranteed domain of attraction, and maximizes the estimated region of the plant states for which the stability and the prescribed quadratic performance are satisfied. A numerical example shows the effectiveness of the present design method.

Detection of nonlinearly distorted signals is an essential problem in telecommunications. Recently, neural network combined conventional equalizer has been used to improve the performance especially in compensating for nonlinear distortions. In this paper, the self-organizing map (SOM) combined with the conventional symbol-by-symbol detector is used as an adaptive detector after the output of the decision feedback equalizer (DFE), which updates the decision levels to follow up the nonlinear distortions. In the proposed scheme, we use the box distance to define the neighborhood of the winning neuron of the SOM algorithm. The error performance has been investigated in both 16 QAM and 64 QAM systems with nonlinear distortions. Simulation results have shown that the system performance is remarkably improved by using SOM detector compared with the conventional DFE scheme.

The linearity of the GaAs Field Effect Transistor (FET) power amplifier is greatly influenced by the nonlinear characteristics of gate-source capacitance (Cgs) and drain-source current (Ids) for the FETs. However, previously suggested analysis methods of GaAs FET non-linearity are mainly focused on the investigations by each individual non-linear component (Cgs or Ids) without considering both non-linear effects. We analyze more accurately the non-linearity of GaAs FETs by considering non-linear effects of Cgs and Ids simultaneously. We also investigate the third-order intermodulation distortion (IMD3) of the GaAs FET in relation to source and load impedances that minimize FET non-linearities. From the simulation results by Volterra-series technique, we show that the least IMD3 is found at the minimum source resistance (RS) and maximum load resistance (RL) in the equivalent output power (Pout) contour. Simulated results are compared with the load and source pull data, with good agreement.

A new approach for extracting significant characteristic within speech signal for distinct speaker is presented. Based on the multiresolution property of wavelet transform, quadrature mirror filters (QMFs) derived by Daubechies is used to decompose the input signal into varied frequency channels. Owning to the uncorrelation property of each resolution derived from QMFs, Linear Predict Coding Cepstrum (LPCC) of lower frequency region and entropy information of higher frequency region for each decomposition process are calculated as the speech feature vectors. In addition, a hard thresholding technique for lower resolution in each decomposition process is also used to remove the effect of noise interference. The experimental result shows that by using this mechanism, not only effectively reduce the effect of noise inference but improve the recognition rate. The proposed feature extraction algorithm is evaluated on MAT telephone speech database for Text-Independent speaker identification using vector quantization (VQ). Some popular existing methods are also evaluated for comparison in this paper. Experimental results show that the performance of the proposed method is more effective and robust than that of the other existing methods. For 80 speakers and 2 seconds utterance, the identification rate is 98.52%. In addition, the performance of our method is very satisfactory even at low SNR.

A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.

We consider the problem of efficient learning of probabilistic concepts (p-concepts) and more generally stochastic rules in the sense defined by Kearns and Schapire and by Yamanishi. Their models extend the PAC-learning model of Valiant to the learning scenario in which the target concept or function is stochastic rather than deterministic as in Valiant's original model. In this paper, we consider the learnability of stochastic rules with respect to the classic 'Kullback-Leibler divergence' (KL divergence) as well as the quadratic distance as the distance measure between the rules. First, we show that the notion of polynomial time learnability of p-concepts and stochastic rules with fixed range size using the KL divergence is in fact equivalent to the same notion using the quadratic distance, and hence any of the distances considered in [6] and [18]: the quadratic, variation, and Hellinger distances. As a corollary, it follows that a wide range of classes of p-concepts which were shown to be polynomially learnable with respect to the quadratic distance in [6] are also learnable with respect to the KL divergence. The sample and time complexity of algorithms that would be obtained by the above general equivalence, however, are far from optimal. We present a polynomial learning algorithm with reasonable sample and time complexity for the important class of convex linear combinations of stochastic rules. We also develop a simple and versatile technique for obtaining sample complexity bounds for learning classes of stochastic rules with respect to the KL-divergence and quadratic distance, and apply them to produce bounds for the classes of probabilistic finite state acceptors (automata), probabilistic decision lists, and convex linear combinations.

A 3 to 5-GHz Si-bipolar quadrature modulator and demodulator are described. Both feature a wideband frequency-doubling 90-degree phase shifter that has a mechanism for self-correction of phase errors caused by an original 90-degree phase-shift network at the half frequency of the carrier. Therefore, the phase shifter produces accurate quadrature carrier signals with doubled frequency. The quadrature modulator and demodulator in 30-GHz Si bipolar technology dissipate 80 mA at a 3-V supply. Image rejection of the modulator is more than 40 dB between 3.2 to 5.2 GHz. The phase and amplitude errors of the demodulator are less than 1.5 degrees and less than 0.15 dB, respectively, between 3.5 to 5.2 GHz. Therefore, both are suitable for either direct conversion or image-rejection transceivers for 5-GHz applications.

This paper examines similarities between the Decision Diffie-Hellman (DDH) assumption and the Quadratic Residuosity (QR) assumption. In addition, we show that many cryptographic protocols based on the QR assumption can be reconstructed using the DDH assumption.

We formalize a model of "demonstration of program result-correctness," and investigate how to prove this fact against possible adversaries, which naturally extends Blum's theory of program checking by adding zero-knowledge requirements. The zero-knowledge requirements are universal for yes and no instances alike.

We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.

This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.

In this paper the application of a linear-quadratic processor is proposed for detection of each user's signal in a direct sequence code division multiple access scheme and, in particular, for W-CDMA systems. In this method, the knowledge of the user of interest, and some statistical knowledge of interfering transmitters' signals are used to detect the desired user's signal without needing exact "a priori" knowledge of the interfering signal parameters such as spreading sequences and signal powers. Parameters of the proposed processor, which are derived so as to maximise the signal-to-interference-plus-noise ratio (SINR), can generally be obtained by solving a system of linear equations for which many effective techniques exist. A model for this detection procedure is developed and shown--through analytical and numerical results--to offer a good compromise between complexity and quality of performance.

Numerical modeling of realistic engineering problems using the FDTD technique often requires smaller cell size, higher simulation accuracy and less computation resources. In this paper, we describe a high performance three-dimensional FDTD algorithm by using non-uniform mesh that allows flexible cell size to improve the accuracy of modeling, and computation resource also can be reduced greatly. In this paper, we will first explain the detailed formulation and algorithm of Non-Uniform Mesh. Next, examination of the reflection error from fine-coarse boundary because of the discontinuity is carried out. Then some test geometry are solved by using both uniform mesh and non-uniform mesh FDTD scheme to validate the results and check the accuracy of solution. We also examine the calculation accuracy due to mesh size ratio, and then investigation of how to determine the fine mesh region surrounding the object for a most small computation error will be carried out in this paper. In addition, the algorithm is demonstrated for several different antenna geometry.

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache). " The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a direct-mapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache.

Triangulations have been one of main research topics in computational geometry and have many applications in computer graphics, finite element methods, mesh generation, etc. This paper surveys properties of triangulations in the two- or higher-dimensional spaces. For triangulations of the planar point set, we have a good triangulation, called the Delaunay triangulation, which satisfies several optimality criteria. Based on Delaunay triangulations, many properties of planar triangulations can be shown, and a graph structure can be constructed for all planar triangulations. On the other hand, triangulations in higher dimensions are much more complicated than in planar cases. However, there does exist a subclass of triangulations, called regular triangulations, with nice structure, which is also touched upon.

Given a plane graph G, we wish to find a drawing of G in the plane such that the vertices of G are represented as grid points, and the edges are represented as straight-line segments between their endpoints without any edge-intersection. Such drawings are called planar straight-line drawings of G. An additional objective is to minimize the area of the rectangular grid in which G is drawn. In this paper first we review known two methods to find such drawings, then explain a hidden relation between them, and finally survey related results.

Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.

A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and VTN respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 VTN respectively. Also the pumping current was increased in the new circuit.

In this paper, the Linear Exponential Quadratic Gaussian with Loop Transfer Recovery (LEQG/LTR) methodology is employed for the design of high performance induction motor servo systems. In addition, we design a speed sensorless induction motor vector controlled driver with both the extended Kalman filter and the LEQG/LTR algorithm. The experimental realization of an induction servo system is given. Compared with the traditional PI and LQG/LTR methods, it can be seen that the system output sensitivity for parameter variations and the rising time for larger command input of the proposed method can be significantly reduced.