A three inputs and single output voltage-mode universal biquadratic filter using only two operational transconductance amplifiers (OTAs) and two capacitors is presented. The new circuits offer several advantages, such as employing the minimum number of active and passive components (two OTAs and two capacitors), the versatility to synthesize highpass, bandpass, lowpass, notch and allpass responses without component matching conditions, high input impedance for bandpass and lowpass filter realizations and good sensitivities performance.

A novel compact T/R (Transmit/Receive) switching circuit for wideband T/R modules has been proposed. It employs quadrature couplers and gate-and-drain-driven HPAs to remove circulators or T/R switches from a conventional T/R module, and T/R switching is made with controlling biasing conditions of the FETs in HPAs. Furthermore, an optimum biasing condition and design of output matching circuit of the HPA have been studied to reduce loss in RX-mode, and the validity of the method has been confirmed by measurements.

A broadband RF front-end having a direct conversion architecture has been developed. The RF front-end consists of two broadband quadrature mixers, a multi-band local oscillator, and a broadband low-noise variable gain amplifier (LNVGA). The mixer achieves broadband characteristics through the incorporation of an in-phase power divider and a 45-degree power divider. The in-phase power divider achieves broadband characteristics through the addition of a compensation capacitor. The 45-degree power divider achieves broadband phase characteristics through the addition of a compensation capacitor and a compensation resistor. The local oscillator, which is composed of two VCOs, two frequency dividers, and four switches, can cover three systems including one FDD system. The LNVGA achieves its broadband characteristics without the use of reactance elements, such as inductors or capacitors. In a trial demonstration, when the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a demodulator experimentally demonstrated an amplitude balance of less than 1.6 dB and a quadrature phase error of less than 3 degrees. When the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a modulator demonstrated an image ratio of less than -30 dBc. The local oscillator demonstrated multi-band characteristics, which are able to cover the target frequencies for three systems (PDC, PHS, 2.4 GHz WLAN). From 900 MHz to 2.5 GHz, the amplifier shows a noise figure of less than 2.1 dB and a gain of 28 1.6 dB.

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.

Recently, neural networks (NNs) have been extensively applied to many signal processing problem due to their robust abilities to form complex decision regions. In particular, neural networks add flexibility to the design of equalizers for digital communication systems. Recurrent neural network (RNN) is a kind of neural network with one or more feedback loops, whereas self-organizing map (SOM) is characterized by the formation of a topographic map of the input patterns in which the spatial locations (i.e., coordinates) of the neurons in the lattice are indicative of intrinsic statistical features contained in the input patterns. In this paper, we propose a novel receiver structure by combining adaptive RNN equalizer with a SOM detector under serious ISI and nonlinear distortion in QAM system. According to the theoretical analysis and computer simulation results, the performance of the proposed scheme is shown to be quite effective in channel equalization under nonlinear distortion.

In this paper, we describe a novel technique to extract a polyhedral description from panoramic range data of a scene taken by a panoramic laser range finder. First, we introduce a reasonable noise model of the range data acquired with a laser radar range finder, and derive a simple and efficient approximate solution of the optimal fitting of a local plane in the range data under the assumed noise model. Then, we compute the local surface normals using the proposed method and extract stable planar regions from the range data by using both the distribution information of local surface normals and their spatial information in the range image. Finally, we describe a method which builds a polyhedral description of the scene using the extracted stable planar regions of the panoramic range data with 360 field of view in a polar coordinate system. Experimental results on complex real range data show the effectiveness of the proposed method.

A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2 4 GB/s at 4 macros. The process cost has been kept low by using VT-MOS circuit technology and taking advantage of a characteristic of dual-gate oxide process technology. A tRAC of 11.6 ns at 2.0 V is achieved using a 'pre-detect redundancy' circuit.

In this paper, a novel continuous complementary sliding control was proposed to improve the tracking performance given the available control bandwidth and the extend of parameter uncertainty. With this control law, the ultimate bound of tracking error was shown to be reduced at least by half, as compared with the conventional continuous sliding control. More strikingly, the proposed control can effectively improve the error transient response during the reaching phase. We presented a composite complementary sliding control scheme for a class of uncertain nonlinear systems including the nonlinear electrohydraulic position servo control system, which will be used as an illustrated example. Simulation results indicated exceptional good tracking performance to step and sine wave reference inputs can be obtained. In addition, the disturbance rejection property of the controller to single-frequency sinusoidal disturbances is also outstanding.

A voltage-mode universal biquadratic filter using single current-feedback amplifier (CFA), two capacitors and three resistors is presented. The new circuit has four inputs and one output and can realize all the standard filter functions, that is, lowpass, bandpass, highpass, notch and allpass filters, without changing the circuit topology. The use of only one current-feedback amplifier simplifiers the configuration.

Embedded-DRAM (eDRAM) power-energy estimation model is proposed for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improves the accuracy of the conventional SRAM power-energy models. The power-energy estimation using SSBA model shows 95% accuracy compared with the transistor level power simulation for three fabricated eDRAMs. The SSBA model combined with the high-level simulator provides fast and accurate system level power-energy estimation of eDRAM.

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.

We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.

We report on the analysis and fabrication of vertical PtSi Schottky source/drain metal oxide semiconductor field effect transistors (MOSFETs), which are suitable for combination with quantum effect devices such as resonant tunneling diodes. Analysis was carried out by one-dimensional approximation of the device structure, WKB approximation of the tunneling probability in Schottky barrier tunneling and self-consistent calculation. Theoretical calculation showed good drivability (750 µA/µm) of this device with tOX = 1 nm and tSi = 5 nm. As a preliminary experiment, devices with a Si channel thickness of 8 nm, 20 nm or 30 nm and a vertical channel length of 55 nm were fabricated. Although the drain current at the "on" state was small due to the thick gate oxide of 8 nm, analysis and measurement showed reasonable agreement with respect to the drivability. Based on the results of theoretical analysis, the device drivability can be much improved by reducing the gate oxide thickness.

In this paper, we consider a network design problem with hub-and-spoke structure. We propose a relaxation technique for the problem where the location of hub nodes is given and decides the allocation of non-hub nodes to one of the hub nodes. We linearize the non-convex quadratic objective function of the original problem, introducing Hitchcock transportation problems defined for each pair of non-hub nodes. We provide two linear relaxation problems, one based on the Hitchcock transportation problems and the other on the dual Hitchcock transportation problems. We show the tightness of the lower bounds obtained by our formulations by computational experiences.

This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.

A practical method of measuring the contact resistance of a phosphorus-doped poly-Si plug formed on a lightly phosphorus-doped diffusion region in DRAM memory cells is described. Contact resistance was obtained electrically, using ordinary contact-chain test structures, by changing the measurement of the substrate bias. This separated the bias-dependent resistance of the lightly doped diffusion layer from the total resistance. The method was used experimentally to evaluate the feasibility of forming low-resistance contacts down to a diameter of 130 nm for giga-bit DRAMs. Electrical measurement showed that reducing the interface resistance between the poly-Si plug and the lightly doped diffusion layer was effective for forming low-resistance contacts, though a specific interface layer could not be detected by TEM observation.

In 1998, Fan and Lei proposed a partially blind signature scheme that could reduce the computation load and the size of the database for electronic cash systems. In this Letter, we show that their scheme could not meet the untraceability property of a blind signature.

The main objective of vehicle suspensions is to improve ride comfort and road holding ability. Though passive suspensions consist of spring and damper, active suspensions adopt an actuator in addition to passive suspensions. In this paper, a quarter car model with an asymmetric hydraulic actuator is used. Moreover, the damping coefficient of the damper, which is changed according to the actuator velocity, is considered. The LPV (Linear Parameter Varying) model is obtained by applying feedback linearization technique. Next, a gain-scheduled controller, based on LQ regulator with different weighting factor, is designed according to the actuator velocity and the stability of the proposed controller is also proved. The effectiveness of the proposed controller is shown by numerical simulations.

In this paper, we propose a probabilistic approach to derive an approximate polyhedral description from range data. We first compare several least-squares-based methods for estimation of local normal vectors and select the most robust one based on a reasonable noise model of the range data. Second, we extract the stable planar regions from the range data by examining the distributions of the local normal vectors together with their spatial information in the 2D range image. Instead of segmenting the range data completely, we use only the geometries of the extracted stable planar regions to derive a polyhedral description of the range data. The curved surfaces in the range data are approximated by their extracted plane patches. With a probabilistic approach, the proposed method can be expected to be robust against the noise. Experimental results on real range data from different sources show the effectiveness of the proposed method.