A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm2 and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.

In this paper, we propose a simple and accurate transfer function model of the power amplifiers for mobile communications. Detail analysis yields a generalized model for AM/AM characteristics in classes AB, B, and C. The analysis includes the effect of drain current variation with input level variation. This model introduces a loadline variation ratio to indicate the change of drain current and to represent the operation classes in a small signal region. Further discussion leads to simplified approximate equations for the AM/AM characteristics, and the estimation procedures for the simplified model parameters. Using the derived procedures, an efficient power amplifier employing pseudomorphic high electron mobility transistor (PHEMT) is fabricated for the 2 GHz band. Finally, the various characteristics given by the model, simulator and measurements are compared and found to agree well in the range of 20 dB below the saturated output level. The model is very effective for characterizing the power amplifiers that are used in linear compensation techniques such as predistortion methods, due to its severe nonlinearity of AM/AM and AM/PM characteristics.

This paper proposes a sensing and a precharge circuit schemes suitable for low-voltage and high-speed DRAM design. The proposed offset-compensated direct sensing scheme improves refresh characteristics as well as speed performance. To minimize the number of control switches for the offset compensation, only the output branches of differential amplifiers are implemented in each bit-line pair with a semi-global bias branch, which also reduces 50-percent of bias current. The addition of the direct sensing feature to the offset-compensated pre-sensing dramatically increases the differential current output. For the fast bit-line equalization, a charge-recycled precharge scheme is proposed to reuse VPP discharging current for the generation of a boosted bias without additional charge pumping. The two circuit schemes were verified by the implementation of a 256 Mb SDRAM with a 0.1 µm dual-doped poly-silicon technology.

In this paper we propose a new blind adaptive compensator associated with the inverse QRD-RLS (IQRD-RLS) algorithm to adaptively estimate the parameters, related to the effects of gain/phase imbalance and DC offsets occur in the Quadrature demodulator, for compensation. In this new approach the power measurement of the received signal is employed to develop the blind adaptation algorithm for compensator, it does not require any reference signal transmitted from the transmitter and possess the fast convergence rate and better numerical stability. To verify the great improvement, in terms of reducing the effects of the imbalance and offset, over existing techniques computer simulation is carried out for the coherent 16 PSK-communication system. We show that the proposed blind scheme has rapidly convergence rate and the smaller mean square error in steady state.

Graph drawing addresses the problem of constructing geometric representation of information and finds applications in almost every branch of science and technology. Efficient algorithms are essential for automatic drawings of graphs, and hence a lot of research has been carried out in the last decade by many researchers over the world to develop efficient algorithms for drawing graphs. In this paper we survey the recent algorithmic results on various drawings of plane graphs: straight line drawing, convex drawing, orthogonal drawing, rectangular drawing and box-rectangular drawing.

This paper describes a novel method of shape matching by means of unification and expansion of local correspondences on the feature points. The method has the ability to simultaneously locate plural similar parts of two-dimensional objects under affine transformation. Furthermore, the method is applicable to the objects partially occluded. Experimental results show that the method yields results that are satisfactory, even for the cases with additions, deletions and local deviations of some feature points.

Temperature dependence of drain current is analyzed in detail in terms of mobility and threshold voltage. From the analyses, it is proved that a point exists that the drain current is fixed without depending on temperature when the MOSFET operates in strong inversion. Applying this characteristic, a CMOS temperature-voltage converter operating in strong inversion with high linearity is proposed. SPICE simulation and experimental results are shown, and the corresponding performances are discussed.

This paper describes feasibility of a proposed fixed wireless access system with CDMA technology. The system adopts a primary modulation of 16 QAM and the same frequency allocation in all cells to improve spectral efficiency. The system capacity is 1 Gbps per cell within 120 MHz bandwidth. The number of available orthogonal codes corresponds to the orthogonal code length in the system. All subscribers can attain an error free condition with output power control in the presence of inter-cell interference. The following two items are considered to examine the proposed system feasibility. 1) A test modem is fabricated, and a back-to-back modem BER performance is measured. An inter-symbol interference (ISI) level of the modem is estimated with the measured performance. 2) A computer simulation of down-link power control is carried out considering inter-cell interference and impairment factors of the power control such as intra-sector interference caused by the ISI and limited ranges of total and relative output power controls. The simulation results show that the proposed system would be feasible because the obtained power penalties caused by the above impairment factors are negligible.

In this paper, using the exact expression for the pairwise error probability derived in terms of the message symbol distance between two message vectors rather than the codeword symbol distance between two transmitted codeword matrices, the exact closed form expressions for the symbol error probability of any linear orthogonal space-time block codes in slow Rayleigh fading channel are derived for QPSK, 16-QAM, 64-QAM, and 2 56-QAM.

We propose using SQP (Sequential Quadratic Programming) to directly recover 3D quadratic surface parameters from multiple views. A surface equation is used as a constraint. In addition to the sum of squared reprojection errors defined in the traditional bundle adjustment, a Lagrangian term is added to force recovered points to satisfy the constraint. The minimization is realized by SQP. Our algorithm has three advantages. First, given corresponding features in multiple views, the SQP implementation can directly recover the quadratic surface parameters optimally instead of a collection of isolated 3D points coordinates. Second, the specified constraints are strictly satisfied and the camera parameters and 3D coordinates of points can be determined more accurately than that by unconstrained methods. Third, the recovered quadratic surface model can be represented by a much smaller number of parameters instead of point clouds and triangular patches. Experiments with both synthetic and real images show the power of this approach.

A low power 16 Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 µm logic -based embedded DRAM process technology. A 0.5 µm2 CUB (apacitor nder it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123 µW are demonstrated at 1.5 V power supply.

The knowledge of a good enclosure of the range of a function over small interval regions allows us to avoid convergence of optimization algorithms to a non-global point(s). We used interval slopes f[X,x] to check for monotonicity and integrated their derivative forms g[X,x], x X by quadratic and Newton methods to obtain narrow enclosures. In order to include boundary points in the search for the optimum point(s), we expanded the initial box by a small width on each dimension. These procedures resulted in an improvement in the algorithm proposed by Hansen.

DC and RF performances of AlGaN/GaN HEMTs are simulated using a two-dimensional device simulator with the material parameters of GaN and AlGaN. The cut-off frequency is estimated as 205 GHz at the gate length of 0.05 µm and the drain breakdown voltage at this gate length is over 10 V. The values are satisfactory for millimeter wavelength power applications. The use of thin AlGaN layers has key importance to alleviate gate parasitic capacitance effects at this gate length.

A new current-mode quadrature oscillator circuit using two differential voltage current conveyors (DVCCs), two grounded capacitors and two grounded resistors is presented. Two high output impedance sinusoid current sources with 90phase difference are available in the proposed circuit. The oscillation condition and oscillation frequency are orthogonally controllable. The use of only grounded capacitors and resistors makes the proposed circuit ideal for integrated circuit implementation. Simulation results are also included.

A low power MPEG-4 video codec LSI with the capability for core profile decoding is presented. A 16-b DSP with a vector pipeline architecture and a 32-b arithmetic unit, eight dedicated hardware engines to accelerate MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing, 20-Mb embedded DRAM, and three peripheral blocks are integrated together on a single chip. MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing are realized with a hybrid architecture consisting of a programmable DSP and dedicated hardware engines at low operating frequency. In order to reduce the power consumption, clock gating technique is fully adopted in each hardware block and embedded DRAM is employed. The chip is implemented using 0.18-µm quad-metal CMOS technology, and its die area is 8.8 mm 8.6 mm. The power consumption is 90 mW at a SP@L1 codec and 110 mW at a CP@L1 decoding.

A new power and bandwidth efficient modulation technique - Superposed Quadrature Quadrature Amplitude Modulation (SQ2AM) - for use in nonlinear satellite channel is presented. SQ2AM technique expands 2-dimensional SQAM signals into 4-dimensional quadrature modulated signals by using orthogonal baseband waveforms and carriers. The power spectrum and BER performance of SQ2AM are analyzed and compared with those of QPSK, SQAM and Q2PSK in a nonlinearly amplified multi-channel environment.

This paper describes an Embedded DRAM Hybrid Macro, which supports various memory specifications. The eDRAM module generator with Hybrid Macro provides more than 120,000 eDRAM configurations. This eDRAM includes a new architecture called Auto Signal Management (ASM) architecture, which automatically adjusts the timing of the control signals for various eDRAM configurations, and reduces the design Turn Around Time. An Enhanced-on-chip Tester performs the maximum 512b I/O pass/fail simultaneous judgments and the real time repair analysis. The eDRAM testing time is reduced to about 1/64 of the time required using the conventional technique. A test chip is fabricated using a 0.18 µm 4-metal embedded DRAM technology, which utilizes the triple-well, dual-Tox, and Co salicide process technologies. This chip achieves a wide voltage range operation of 1.2 V at 100 MHz to 1.8 V at 200 MHz.

In this paper, we propose a TCAD driven hot carrier reduction methodology of 3.3 V I/O pMOSFETs design. The hot carrier reliability of surface channel I/O pMOSFET having drain structure in common with core devices has a critical issue. It is substantially important for the high-reliability devices to reduce both drain avalanche and channel hot hole components. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and drive current (ION), SDE/HALO of both core and I/O transistors can be totally optimized for reduction of process-steps and/or photo-masks.

Small-size MOSFETs are becoming core devices in RF applications because of improved high frequency characteristics. For reliable design of RF integrated circuits operating at the GHz range, accurate modeling of small-size MOSFET characteristics is indispensable. In MOSFETs with reduced gate length (Lg), the lateral field along the MOSFET channel is becoming more pronounced, causing short-channel effects. These effects should be included in the device modeling used for circuit simulation. In this work, we investigated the effects of the field gradient in the gate-drain capacitance (Cgd). 2-Dimensional (2D) simulations done with MEDICI show that the field gradient, as it influences the channel condition, induces a capacitance which is visible in the MOSFET saturation operation. Changes in Cgd is incorporated in the modeling by an induced capacitance approach. The new approach has been successfully implemented in the surface-potential based model HiSIM (Hiroshima-university STARC IGFET Model) and is capable of reproducing accurately the measured Cgd-Lg characteristics, which are particularly significant for pocket-implant technology. Results show that pocket-implantation introduces a steep potential increase near the drain region, which results to a shift of the Cgd transition region (from linear to saturation) to lower bias voltages. Cgd at saturation decreases with Lg due to steeper surface potential and increased impurity concentration effects at reduced Lg.

In this paper, a new narrowband beamformer with derivative constraint is developed for wideband and coherent jammers suppression. The so-called IQML algorithm with linear constraint, which is used to estimate the unknown directions of the jammers in signal-free environment, is shown to be an inappropriate constraint estimator. In this paper, a new IQML algorithm with a norm constraint is considered, which is a consistent estimator and can be used to achieve desired performance. It can be also employed in the CDMA system for MAI suppression. We show that it outperforms the approach with the linear constraint used in the narrowband beamformer, in terms of directional pattern, output SINR and nulling capability for wideband and coherent jammers suppression.