A new concept of "an imperfect singular solution" is defined as an approximate solution which becomes a singular solution by adding a suitable small perturbation to the original equations. A numerical method is presented for proving the existence of imperfect singular solutions of nonlinear equations with guaranteed accuracy. A few numerical examples are also presented for illustration.
Mikio IWAMURA Seizo SEKI Kazuhiro MIYAUCHI
The characteristics of the decision feedback carrier recovery loop (DFL) for conventional QPSK signaling is evaluated experimentally through measurements of the carrier-to-noise ratio of the regenerated carrier, lock range, acquisition waveforms and bit error rates. The results show that the DFL hardly exhibits inferiority to the ideal synchronization by designing the loop natural frequency adequately small. The DFL is shown superb in carrier tracking.
In this paper, a new multicast routing method for layered streams is proposed. This method is an extension of the weighted greedy algorithm (WGA) and uses two kinds of weight values to refine the link distance. It can cope with dynamic change in the group members without multicast tree re-construction. The method is compatible with the RSVP and can be utilized in existing shared tree type routing protocols such as CBT and PIM sparse mode. The network resources can be utilized efficiently; furthermore, the loss rate of member's requests to receive more layers can be reduced by this routing method when a sufficient number of nodes have the packet filtering function and a sufficient number of hops is permitted.
Kyung-Woo KANG Kwang-Moo CHOE Min-Soo JUNG
In this paper, we propose an efficient method of constructing states in bottom-up tree pattern matching with dynamic programming technique for optimal code generation. This method can be derived from precomputing the analysis which is needed for constructing states. The proposed scheme is more efficient than other scheme because we can avoid unfruitful tests in constructing states at compile time. Furthermore, the relevant analyses needed for this proposal are largely achieved at compile-compile time, which secures actual efficiency at compile time.
Atsushi KAMITANI Shigetoshi OHSHIMA
The magnetic shielding performance of the high-Tc superconducting (HTS) plate in a mixed state has been investigated numerically. By taking account of the crystallographic anisotropy of the HTS plate, the axisymmetric shielding plate is assumed to have a multiple thin-layer structure. Under the assumptions, the governing equations of the shielding current density can be expressed in terms of a scalar function. The numerical code to integrate the equation has been developed and, by use of the code, the shielding current density and the damping coefficient are calculated for the axisymmetric HTS plate in a mixed state. The results of computations show that the shielding current density localizes around the edge under the high-frequency magnetic field. With an increasing frequency of the applied magnetic field, the localization becomes remarkable and the shielding current density becomes larger until the flux flow occurs. In addition, the magnetic shielding performance of the HTS plate drastically changes with time under the low-frequency magnetic field below 100 Hz, whereas it is almost time-independent under the high-frequency magnetic field. Moreover, it turns out that the HTS plate can shield ac magnetic fields with a high frequency even if it remains in a mixed state.
Kazuyoshi TAKAGI Naofumi TAKAGI
Two algorithms for minimum cut linear arrangement of a class of graphs called p-q dags are proposed. A p-q dag represents the connection scheme of an adder tree, such as Wallace tree, and the VLSI layout problem of a bit slice of an adder tree is treated as the minimum cut linear arrangement problem of its corresponding p-q dag. One of the two algorithms is based on dynamic programming. It calculates an exact minimum solution within nO(1) time and space, where n is the size of a given graph. The other algorithm is an approximation algorithm which calculates a solution with O(log n) cutwidth. It requires O(n log n) time.
Technologies used to characterize and compensate nonlinearities in microwave power amplifiers are discussed. First, a complex power series representation that allows both amplitude and phase nonlinearities to be dealt with simultaneously is proposed, and in order to estimate the 3rd-order complex coefficient phase of practical amplifiers, two kinds of experimental measurement methods are proposed. Next, the fundamental circuit configuration of IF cuber predistortion linearizer that compensates 3rd-order intermodulation distortion is derived from a nonlinear analysis using complex power series representation. Two practical cuber predistorters for the 6-GHz TWTA and the 800-MHz FET-PA are demonstrated. Moreover, the unique nonlinear compensation technology of side-band inversion is introduced for microwave relay system using TWTAs. Finally, the self-adjusting feed-forward (SAFF)-PA developed for digital cellular base stations is reviewed.
Makoto ISHIKAWA Naotake KAMIURA Yutaka HATA
This paper proposes a thresholding based segmentation method aided by Kleene Algebra. For a given image including some regions of interest (ROIs for short) with the coherent intensity level, assume that we can segment each ROI on applying thresholding technique. Three segmented states are then derived for every ROI: Shortage denoted by logic value 0, Correct denoted by 1 and Excess denoted by 2. The segmented states for every ROI in the image can be then expressed on a ternary logic system. Our goal is then set to find "Correct (1)" state for every ROI. First, unate function, which is a model of Kleene Algebra, based procedure is proposed. However, this method is not complete for some cases, that is, correctly segmented ratio is about 70% for three and four ROI segmentation. For the failed cases, Brzozowski operations, which are defined on De Morgan algebra, can accommodate to completely find all "Correct" states. Finally, we apply these procedures to segmentation problems of a human brain MR image and a foot CT image. As the result, we can find all "1" states for the ROIs, i. e. , we can correctly segment the ROIs.
Packet contention is one of the fundamental problems that must be overcome in designing packet switches. In banyan network, which has multistage interconnection structure of many small switch elements, we must be concerned with output port conflicts and internal collisions. Dilated banyan network which provides multiple path for internal link can reduce packet loss due to internal collisions in loss system. However, under hot-spot traffic higher packet loss probability is measured at the hot-spot port and the ports close to the hot-spot as coefficient h increases due to the heavy traffic to hot-spot port. In order to moderate the packet loss probability at the hot-spot port we propose the method to disperse the packets which concentrate on the hot-spot route by altering address field of a half of incoming packets. These packets are switched along detour routes. Thus, the traffic concentration toward hot-spot is mitigated and the packet loss probability at the hot-spot port is moderated.
Jin-Nam PARK Tsuyoshi USAGAWA Masanao EBATA
This paper proposes an adaptive microphone array using blind deconvolution. The method realizes an signal enhancement based on the combination of blind deconvolution, synchronized summation and DSA (Delay-and-Sum Array) method. The proposed method improves performance of estimation by the iterative operation of blind deconvolution using a cost-function based on the coherency function.
In this paper, the correlation properties are used to develop two efficient encoding schemes for speech line spectrum frequency (LSF) parameters. The first scheme (1D KL), which exploits the intraframe correlation, is based on one-dimensional Karhunen-Loeve (KL) transformation; the second scheme, which requires some coding delays to further utilize the interframe correlation, uses two-dimensional (2D KL) transform in the frequency domain or one-dimensional KL transform co-operating with DPCM in the time domain. Moreover, since the KL transform is globally optimal, which is sensitive to the change of input data statistics, further two adaptive transform coding systems are also investigated in this paper. The performance of all systems for different bit rates is investigated and adequate comparisons are made. It is shown that the gain of using KL transformation to exploit the intraframe and interframe correlation is 3 and 4 bits/speech frame, respectively.
Munehiro NAMBA Yoshihisa ISHIDA
The conventional linear prediction can be viewed as a constrained blind equalization problem that has gained a lot of interests along with development of telecommunication networks. Because the blind equalization or deconvolution is a general framework of the inverse problem, the reliable and faster algorithm is requested in many applications. This paper proposes an orthogonal wavelet transform domain realization of a blind equalization technique termed as EVA, and presents an application to speech analysis. An orthogonal transformation has no influence to the equalization result in general, but we show that a particular wavelet makes the matrix in EVA nearly lower triangular that promotes the faster convergence in the estimation of maximum eigenvalue and its associate vector in EVA iteration. The experiments with the Japanese vowels show that the the proposed method effectively separates the glottis and vocal tract information, hence is promising for speech analysis.
The main issues of the next generation Internet are high performance multicast, security and QoS (Quality of Service). The network layer multicast is accepted as a powerful solution to reduce communication overhead in networks as well as hosts. Although a lot of multicast routing protocols have been developed and have worked for the current Internet, they have drawbacks in scalability, reliability and network load balancing. In this paper, we propose an enhanced multicast routing protocol called DCBT (Decentralized Core based Tree), which includes some features of CBT (Core Based Tree), PIM-SM (Protocol Independent Multicast-Sparse Mode) and BGMP (Border Gateway Multicast Protocol). Fundamentally DCBT differs from those in that it covers not only intra-region but also inter-region multicast. RNs (Regional networks) have their intra-region shared trees, which are interconnected by an inter-region shared tree for a multicast group. New two concepts are introduced: the one is RBTS (Region Based Tree Switching) to achieve network load balancing and the other is to redefine TOS (Type Of Service) byte to make special multicast routing decision. In addition, the effect of core location is given by changing its position within an RN. Finally we provide the performance evaluation of DCBT by OPNET network simulator over a real scale network model.
Masataka NAKAMURA Katsuhito KOUNO Toshitaka YAMATO Kazuhiro SAKIYAMA
In order that the speech recognition system might have a high performance in the noisy environment, the directional microphone arrays at the input of the system have been broadly investigated. The purpose of this study is to develop a new wide-band directional microphone system in view of advancing to an adaptive one afterwards. In the proposed system, three microphones are arranged on a straight line and the beamforming is accomplished in such a way that the output value of the middle microphone is added to the integrated value of the difference between two microphones at both sides. In this study, the signal processing of microphone outputs is implemented by using active RC circuits. Finally, the objective directivity can be experimentally obtained in wide frequency ranges required for the speech recognition.
Masaki HIROSE Keiji KISHINE Haruhiko ICHINO Noboru ISHIHARA
This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.
Hitoshi OKAMURA Masaharu SATO Satoshi NAKAMURA Shuji KISHI Kunio KOKUBU
This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.
Feedback of class memberships is incorporated into multimodal pattern classifiers and their unsupervised learning algorithm is presented. Classification decision at low levels is revised by the feedback information which also enables the reconstruction of patterns at low levels. The effects of the feedback are examined for the McGurk effect by using a simple model.
A novel method for the radiated immunity test is proposed. The method is to generate controlled electromagnetic fields applying in arbitrary directions to an under test. The fields rotate at a low speed controlled electrically so that the immunity characteristics may be known in more detail. The primal characteristics of the fields generated by a trial benchtop setup are investigated.
Fukashi MORISHITA Yasuo YAMAGUCHI Takahisa EIMORI Toshiyuki OASHI Kazutami ARIMOTO Yasuo INOUE Tadashi NISHIMURA Michihiro YAMADA
It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.
Yasuaki SUMI Kouichi SYOUBU Shigeki OBOTE Yutaka FUKUI Yoshio ITOH
The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.