A high-speed static logic circuit, the 1:8 demultiplexer (DEMUX), fabricated using single-gate CMOS technology (single-gate means the structure consisting of n+ poly-Si gate for both NMOS and PMOS transistors) has been demonstrated. To suppress short-channel effects in PMOS transistors, we only used the low-energy ion implantation (I/I) of BF2 at 10 keV for counterdoping of the channel and that at 5 keV for source/drain (S/D) extension. To control the threshold voltage Vth of PMOS transistors precisely, the channel dopants were implanted after the growth of the gate oxide because of the suppression of the transient-enhanced diffusion (TED) of boron, and the suppression of boron out-diffusion. A tree-type 1:8 DEMUX circuit composed of 0. 134 µm gate CMOS transistors operates at a high speed of 3.1 GHz and consumes a low power of 35.5 mW/GHz at VDD = 2.0 V. In this single-gate CMOS circuit, down to this small gate length, the maximum operating frequency of the DEMUX circuit increases proportionally with an increase of the inverse of the gate length without an increase of power consumption per GHz. At a practical 2.48832 Gb/s operation, the power consumption was 88 mW, and the phase margin between the input clock signal and the input data signal was 260 ps. It is suggested that a circuit composed of a single-gate CMOS transistor with 0.15 µm gate generation can be applicable to high speed ICs.

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

In this paper, we briefly review the recent research on CMOS gigahertz-rate communication circuits. Then, we describe design innovations we have made to overcome limitations on communication speed. Using 0. 25-µm CMOS technology, we developed a 4.25-Gb/s Fibre Channel transceiver that features an asynchronous tree-type 1 : 8 demultiplexer and an 8-bit-to-10-bit frequency-conversion architecture. And using 0. 15-µm CMOS technology, we developed an 11. 8-GHz frequency divider that introduces the novel idea of a hysteresis-controlled latch (HC-latch). With these results, we discuss high-speed LSI design issues and future prospects.

A problem of obtaining an optimal file transfer on a file transmission net N is to consider how to distribute, with a minimum total cost, copies of a certain file of information from some vertices to others on N by the respective vertices' copy demand numbers. This paper proves such a problem to be NP-hard in general.

Design and evaluation of a high-performance switch architecture for free-space photonic switching systems is described. The switch is constructed of 22 switching elements and employs special multistage interconnection patterns. The connection setup algorithm and the control procedure at the switching elements are based on a "rerouting algorithm." Performance analysis shows that the blocking probability of the switch is easily controlled by increasing the number of switching stages. Example implementations of this switch are shown in which birefringent plates, polarization controllers, etc. are used.

Design and evaluation of a high-performance switch architecture for free-space photonic switching systems is described. The switch is constructed of 22 switching elements and employs special multistage interconnection patterns. The connection setup algorithm and the control procedure at the switching elements are based on a "rerouting algorithm."" Performance analysis shows that the blocking probability of the switch is easily controlled by increasing the number of switching stages. Example implementations of this switch are shown in which birefringent plates, polarization controllers, etc. are used.

In learning of feed-forward neural networks, so-called 'training error' is often minimized. This is, however, not related to the generalization capability which is one of the major goals in the learning. It can be interpreted as a substitute for another learning which considers the generalization capability. Admissibility is a concept to discuss whether a learning can be a substitute for another learning. In this paper, we discuss the case where the learning which minimizes a training error is used as a substitute for the projection learning, which considers the generalization capability, in the presence of noise. Moreover, we give a method for choosing a training set which satisfies the admissibility.

We propose two lockout-free (starvation-free) mutual exclusion algorithms for the asynchronous multi-writer/reader shared memory model. The first algorithm is a modification of the well-known tournament algorithm for the mutual exclusion problem. By the modification we can speed up the original algorithm. The running time of the modified algorithm from the entrance of the trying region to the entrance of the critical region is at most (n-1)c+O(nl), where n is the number of processes, l is an upper bound on the time between successive two steps of each process, and c is is an upper bound on the time that any user spends in the critical region. The second algorithm is a further modification of the first algorithm. It is designed so that some processes have an advantage of access to the resource over other processes.

Critical properties of real-time embedded systems must be verified before these systems are deployed as failing to meet these properties may cause considerable property damages and/or human casualties. Although Statechart is one of the most popular languages for modeling behavior of real-time systems, proof systems and analysis tools for Statechart so far are in research and do not fully support the semantics of the original Statechart, or have limited capabilities for proving real-time properties. This paper introduces a toolset ASADAL/PROVER for verifying temporal properties of Statechart extended with justice and compassion properties. ASADAL/PROVER is composed of two subsystems, RTTL-Prover and Model-Checker. The RTTL-Prover converts Statechart specifications into real-time temporal logic (RTTL) formulas of Ostroff, and then checks if the formulas satisfy a temporal property (also in RTTL) using theorem proving techniques. The Model-Checker supports verification of a predefined set of real-time properties using a model checking technique. The RTTL-Prover can support verification of any real-time properties as long as they can be specified in RTTL and, therefore, messages generated by the tool are general and may not be of much help in debugging Statechart specifications. The Model-Checker, however, can provide detailed information for debugging. ASADAL/PROVER has been applied successfully to some experimental systems. One of on-going researches in this project is to apply the symbolic model-checking technique by[3]to support Statecharts with a much larger global-state space. We are also extending the types of temporal properties supported by the Model-Checker.

High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.

In order to exploit fully the frequency diversity benefits of multicarrier modulation (MCM), and the very nature of the frequency selective radio channel, we investigate an erasure decoded π/4 QDPSK MCM (ED-MCM) by employing simple Hamming (block) code. We propose the threshold-free criteria, i. e. relative minimum receive power test (RMRPT) and relative maximum decision error test (RMDET) for erasure generation and evaluate ED-MCM's performance by applying these tests to average received power, average decision error, instantaneous symbol/bit decision errors. At a normalized delay spread of 1/64, computer simulation results indicate a coding gains of 6.0 - 7.0 dB with ED-MCM at a BER of 10-3. RMDET/RMRPT based erasure decoding yields a 1.5 - 2.5 dB improvement over the conventional forward error correction (FEC) decoding at a BER of 10-5. The simulation results at other normalized delay spreads, i. e. , 1/32, 1/16 are also obtained. The erasure criteria (RMRPT and RMDET) applied to average values of received power/decision error yield consistently better performance over error only decoding. The results indicate that the erasure decoding based on relative (threshold-free) measures clearly promises an improved performance of the MCM system.

Decision trees are used as a convenient means to explain given positive examples and negative examples, which is a form of data mining and knowledge discovery. Standard methods such as ID3 may provide non-monotonic decision trees in the sense that data with larger values in all attributes are sometimes classified into a class with a smaller output value. (In the case of binary data, this is equivalent to saying that the discriminant Boolean function that the decision tree represents is not positive. ) A motivation of this study comes from an observation that real world data are often positive, and in such cases it is natural to build decision trees which represent positive (i. e. , monotone) discriminant functions. For this, we propose how to modify the existing procedures such as ID3, so that the resulting decision tree represents a positive discriminant function. In this procedure, we add some new data to recover the positivity of data, which the original data had but was lost in the process of decomposing data sets by such methods as ID3. To compare the performance of our method with existing methods, we test (1) positive data, which are randomly generated from a hidden positive Boolean function after adding dummy attributes, and (2) breast cancer data as an example of the real-world data. The experimental results on (1) tell that, although the sizes of positive decision trees are relatively larger than those without positivity assumption, positive decision trees exhibit higher accuracy and tend to choose correct attributes, on which the hidden positive Boolean function is defined. For the breast cancer data set, we also observe a similar tendency; i. e. , positive decision trees are larger but give higher accuracy.

We analyze the security of iterated 2m-bit hash functions with rate 1 whose round functions use a block cipher with an m-bit input (output) and a 2m-bit key. We first show a preimage attack with O(2m) complexity on Yi and Lam's hash function of this type. This means that their claim is wrong and it is less secure than MDC-2. Next, it is shown that a very wide class of such functions is also less secure than MDC-2. More precisely, we prove that there exist a preimage attack and a 2nd preimage attack with O(2m) complexity and a collision attack with O(23m/4) complexity, respectively. Finally, we suggest a class of hash functions with a 2m-bit hashed value which seem to be as secure as MDC-2.

Simple expressions for constriction resistance of multitude conducting spots were analytically formulated by Greenwood. These expressions, however, include some approximations. Nakamura presented that the constriction resistance of one circular spot computed using the BEM is closed to Maxwell's exact value. This relative error is only e=0. 00162 [%]. In this study, the constriction resistances of two, five and ten conducting spots are computed using the boundary element method (BEM), and compared with those obtained using Greenwood's expressions. As the conducting spots move close to each other, the numerical deviations between constriction resistances computed using Greenwood's expressions and the BEM increase. As a result, mutual resistance computed by the BEM is larger than that obtained from Greenwood's expressions. The numerical deviations between the total resistances computed by Greenwood's expressions and that by the BEM are small. Hence, Greenwood's expressions are valid for the total constriction resistance calculation and can be applied to problems where only the total resistance of two contact surfaces, such as a relay and a switch, is required. However, the numerical deviations between the partial resistances computed by Greenwood's expression and that by the BEM are very large. The partial resistance calculations of multitude conducting spots are beyond the applicable range of Greenwood's expression, since Greenwood's expression for constriction resistance of two conducting spots is obtained by assuming that the conducting spots are equal size. In particular, the deviation between resistances of conducting spots, which are close to each other, is very large. In the case of partial resistances which are significant in semiconductor devices, Greenwood's expressions cannot be used with high precision.

The distributions of a spectral intensity of the breaking arc between silver contacts in DC 45-66 V/2.5-5.0 A circuits have been measured using a high-speed color video. As a result, a cathode brightening spot, which has a high spectral intensity, exists near the cathode surface. The cathode brightening spot expands with the increase of the contact gap, but its length expands until about 18µm. When the contact gap spreads over about 180 µm, a dark positive column appears and grows between the cathode brightening spot and the anode surface. The higher the interrupted current is, the larger the diameter of the cathode brightening spot will be. The maximum diameter of cathode brightening spot is 500 µm under these experiments.

The static fatigue parameters of plastic sleeves are determined by dynamic fatigue and destructive tests. The failure probability and lifetime of the plastic sleeve are estimated by using these parameters. No failure is expected for 20 years if the plastic sleeve is used in a normal atmosphere (23, 60%RH) and hot water (50).

With the introduction of ATM technology, service providers around the world have actively engaged in offering high bandwidth services. Currently, services, such as T1/E1, T3/E3 circuit emulation, are made available to large-volume account users. However, more advanced services, such as multimedia applications, have demanded not just high bandwidth but also flexible rate adaptation with quality-of-service (QoS) guarantee. To support the above service requirements, sophisticated network planning and engineering procedures should be taken. In the past few years, we have conducted various researches on developing the engineering strategies for resource control and management to support multi-rate service offering. We have also looked into the design details of connection control and management for achieving the QoS requirement. We considered the service quality of the underlying transport in regard with the QoS management. In this paper, we will outline those results and give an overview description about the proposed framework.

In this paper, we consider the applicability of turbo code for future third generation (3G) mobile telecommunication systems. Futhermore, we propose a simple method of estimating the channel variance which is necessary for the MAP (Maximum A Posteriori) decoding algorithm. We compare the performance of turbo code with a known channel variance, conventional variance estimate and variance estimated by our proposed technique. We show that our variance estimation scheme is adequate for 3G WB-CDMA mobile systems without degradation of turbo code performance.

In this paper, we present an analysis of the microstrip lines whose strip conductors are of various cross-sections, such as rectangular cross-section, triangle cross-section, and half-cycle cross-section. The method employed is the boundary integral equation method (BIEM). Numerical results for these microstrip lines demonstrate various shape effects of the strip conductor on the characteristics of lines. The processing technique on the convergence of the Green's function is also described.

This paper describes a new method for permittivity measurement using microwave free-space technique. The general consideration is to measure the amplitudes of transmission and reflection coefficients and calculate the permittivity from the measurement values. Theoretical analysis shows that the permittivity of the sample can be calculated solely from the measurement values of the amplitudes of transmission and reflection coefficients when the sample is prepared with so large attenuation that the multiple reflections between the two surfaces of the sample can be neglected. Using this method, the permittivity measurement can be performed without reflection influence, and on-line measurement of the permittivity becomes possible because the permittivity can be measured instantaneously and without contact with the material.